| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ecp5: Add simulation equivalence check for Diamond FF implementations | David Shah | 2019-08-30 | 3 | -0/+87 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. | whitequark | 2019-08-30 | 5 | -95/+60 |
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| * | ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives. | whitequark | 2019-08-30 | 1 | -35/+20 |
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| * | ecp5: add missing FD primitives. | whitequark | 2019-08-30 | 2 | -72/+76 |
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| * | ecp5: fix CEMUX on IFS/OFS primitives. | whitequark | 2019-08-30 | 2 | -18/+18 |
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| * | Rename boxes too | Eddie Hung | 2019-08-29 | 3 | -3/+3 |
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| * | Do not overwrite LUT param | Eddie Hung | 2019-08-28 | 1 | -1/+0 |
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| * | Trailing comma | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| * | Adapt to $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-28 | 1 | -3/+5 |
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| * | Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" | Eddie Hung | 2019-08-28 | 1 | -0/+45 |
| | | | | | This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f. | ||||
| * | Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with | Eddie Hung | 2019-08-28 | 1 | -45/+0 |
| | | | | | CARRY_WRAPPER in the same way since I0 and I3 could be used | ||||
| * | Update box size and timings | Eddie Hung | 2019-08-28 | 3 | -12/+12 |
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| * | Update to new $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-28 | 1 | -11/+8 |
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| * | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 |
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| * | Merge pull request #1332 from YosysHQ/dave/ecp5gsr | David Shah | 2019-08-28 | 6 | -54/+212 |
| |\ | | | | | ecp5: Add GSR and SGSR support | ||||
| | * | ecp5: Add GSR support | David Shah | 2019-08-27 | 6 | -54/+212 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 |
| | | | | | | | | | Fixes #1331. | ||||
| * | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
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| | * | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 |
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| * | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| | * | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
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| * | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 3 | -18/+36 |
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| | * | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 3 | -14/+28 |
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| * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 29 | -299/+1059 |
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| | * | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge pull request #1289 from mmicko/anlogic_fixes | Clifford Wolf | 2019-08-22 | 5 | -91/+162 |
| | |\ | | | | | | | Anlogic fixes and optimization | ||||
| | | * | Merge remote-tracking branch 'upstream/master' into anlogic_fixes | Miodrag Milanovic | 2019-08-18 | 7 | -165/+37 |
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| | | * | | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 5 | -91/+162 |
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| | * | | | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Merge pull request #1281 from mmicko/efinix | Clifford Wolf | 2019-08-22 | 9 | -0/+798 |
| | |\ \ \ | | | | | | | | | | | Initial support for Efinix Trion series FPGAs | ||||
| | | * | | | Fix formating | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
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| | | * | | | one bit enable signal | Miodrag Milanovic | 2019-08-11 | 1 | -1/+1 |
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| | | * | | | fix mixing signals on FF mapping | Miodrag Milanovic | 2019-08-11 | 1 | -4/+4 |
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| | | * | | | Replaced custom step with setundef | Miodrag Milanovic | 2019-08-11 | 3 | -91/+1 |
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| | | * | | | Fixed data width | Miodrag Milanovic | 2019-08-11 | 1 | -2/+2 |
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| | | * | | | Adding new pass to fix carry chain | Miodrag Milanovic | 2019-08-11 | 3 | -0/+124 |
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| | | * | | | cleanup | Miodrag Milanovic | 2019-08-11 | 1 | -4/+7 |
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| | | * | | | Fix CO | Miodrag Milanovic | 2019-08-09 | 1 | -26/+24 |
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| | | * | | | Merge remote-tracking branch 'upstream/master' into efinix | Miodrag Milanovic | 2019-08-09 | 9 | -267/+303 |
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| | | * | | | | clock for ram trough gbuf | Miodrag Milanovic | 2019-08-04 | 1 | -0/+6 |
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| | | * | | | | Added bram support | Miodrag Milanovic | 2019-08-04 | 6 | -1/+260 |
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| | | * | | | | Custom step to add global clock buffers | Miodrag Milanovic | 2019-08-03 | 4 | -1/+129 |
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| | | * | | | | Initial EFINIX support | Miodrag Milanovic | 2019-08-03 | 5 | -0/+370 |
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| | * | | | | | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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| | * | | | | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | [WIP] synth xilinx renaming, as per #1184 | ||||
| | | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 26 | -343/+629 |
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| | | * | | | | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
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| | | * | | | | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
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| | * | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 3 | -19/+41 |
| | |\ \ \ \ \ \ | | |_|/ / / / | |/| | | | | | Refactor abc9 to use port attributes, not module attributes | ||||
| | | * | | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 3 | -6/+6 |
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index : iCE40/yosys | |
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