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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-143-4/+198
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-148-763/+129
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
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* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
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* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
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* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
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* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
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* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
| | | | This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
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* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
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* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
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* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
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* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
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* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
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* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-145-369/+5
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* Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-142-7/+30
|\ | | | | ast: swap range regardless of range_left >= 0
| * techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-052-7/+30
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* | ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
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* | ice40: fix whitespaceEddie Hung2020-05-121-15/+14
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* | ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-078-52/+143
| | | | | | | | | | | | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-043-11/+34
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* gowin,ecp5: remove generated files in `make clean`.whitequark2020-04-242-2/+10
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* intel_alm: cleanup duplicationDan Ravensloft2020-04-245-113/+64
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* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+10
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* ecp5: ecp5_gsr to skip cells that don't have GSR parameter againEddie Hung2020-04-221-1/+1
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* xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
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* Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-222-12/+6
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* intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127
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* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-3/+3
| | | | Fixes #1822.
* ecp5: Force SIGNED ports to be 1 bitDavid Shah2020-04-161-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix the truth table for $_SR_* cells.Marcelina Kościelnicka2020-04-153-26/+21
| | | | | | | | This brings the documented behavior for these cells in line with $_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S. The models were already reflecting that behavior. Also get rid of sim-synth mismatch in the models while we're at it.
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-159-10/+1
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* synth_intel_alm: VQM supportDan Ravensloft2020-04-152-6/+3
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* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1518-1/+1453
| | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-2/+137
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
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| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
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| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-062-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+1
| | | | | | | | LSE/Synplify use case insensitive matching.
| * ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* | Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-035-13/+121
|\ \ | | | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * | cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmpEddie Hung2020-04-031-1/+1
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| * | cmp2lcu: fail if `LUT_WIDTH < 2Eddie Hung2020-04-031-1/+1
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| * | synth: only techmap cmp2{lut,lcu} if -lutEddie Hung2020-04-031-1/+1
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| * | synth: use +/cmp2lcu.v in generic 'synth' tooEddie Hung2020-04-031-2/+2
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| * | Cleanup +/cmp2lut.vEddie Hung2020-04-031-8/+0
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| * | synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
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| * | +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-33/+42
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