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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-2014-200/+97
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| * Merge pull request #1209 from YosysHQ/eddie/synth_xilinxEddie Hung2019-08-204-16/+19
| |\ | | | | | | [WIP] synth xilinx renaming, as per #1184
| | * Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-2026-343/+629
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| | * | Update Makefile tooEddie Hung2019-07-181-2/+2
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| | * | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-183-14/+17
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| * | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-203-19/+41
| |\ \ \ | | |_|/ | |/| | Refactor abc9 to use port attributes, not module attributes
| | * | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-193-6/+6
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| | * | Update abc_* attr in ecp5 and ice40Eddie Hung2019-08-162-11/+21
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| | * | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modulesEddie Hung2019-08-161-8/+20
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| * | | Merge branch 'master' into eddie/pr1266_againwhitequark2019-08-181-15/+5
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| | * \ \ Merge pull request #1250 from bwidawsk/masterEddie Hung2019-08-161-15/+5
| | |\ \ \ | | | |/ / | | |/| | techlibs/intel: Clean up Makefile
| | | * | techlibs/intel: Clean up MakefileBen Widawsky2019-08-051-15/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use GNU make's foreach iterator and remove nonexistent files. Gmake is already a requirement of the build system. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPEREddie Hung2019-08-121-1/+1
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| * | | | Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-126-150/+32
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
* | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-151-1/+5
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| * | | | xilinx: Rework labels for faster Verilator testingDavid Shah2019-08-131-1/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Only swap ports if $mul and not $__mulEddie Hung2019-08-131-1/+1
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* | | | | Add assign PCOUT = P to DSP48E1Eddie Hung2019-08-131-0/+2
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* | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-132-145/+111
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* | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-126-28/+50
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| * | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-106-32/+150
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| * | | Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-105-20/+14
| |\ \ \ | | | | | | | | | | Cleanup a few barnacles across codebase
| | * | | substr() -> compare()Eddie Hung2019-08-071-3/+3
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| | * | | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-1/+1
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| | * | | Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-117/+252
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| | * | | | stoi -> atoiEddie Hung2019-08-073-3/+3
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| | * | | | Fix spacingEddie Hung2019-08-061-3/+3
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| | * | | | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
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| | * | | | Make liberal use of IdString.in()Eddie Hung2019-08-061-14/+8
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| * | | | | Merge pull request #1270 from YosysHQ/eddie/alu_lcu_docClifford Wolf2019-08-101-8/+36
| |\ \ \ \ \ | | | | | | | | | | | | | | Add a few comments to document $alu and $lcu
| | * | | | | Reformat so it shows up/looks nice when "help $alu" and "help $alu+"Eddie Hung2019-08-091-25/+34
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| | * | | | | A bit more on where $lcu comes fromEddie Hung2019-08-091-0/+2
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| | * | | | | Add more commentsEddie Hung2019-08-091-4/+18
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| | * | | | | Add a few comments to document $alu and $lcuEddie Hung2019-08-081-9/+12
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| * | | | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-2/+0
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| * | | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-10/+17
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| * | | | | Add testEddie Hung2019-08-071-1/+10
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| * | | | | Remove ice40_unlutEddie Hung2019-08-072-107/+0
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| * | | | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* | | | | Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
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* | | | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-0/+2
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* | | | | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
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* | | | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-083-1/+36
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* | | | | Combine techmap callsEddie Hung2019-08-081-2/+1
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* | | | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
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* | | | | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
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* | | | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
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* | | | | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-087-125/+278
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