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| * | | | | | | | | | | | | Fix spacingEddie Hung2019-07-261-3/+3
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| * | | | | | | | | | | | | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
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| * | | | | | | | | | | | | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
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| * | | | | | | | | | | | | Remove debugEddie Hung2019-07-221-1/+0
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| * | | | | | | | | | | | | Rename according to vendor doc TN1295Eddie Hung2019-07-221-0/+1
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| * | | | | | | | | | | | | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
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| * | | | | | | | | | | | | Use minimum sized width wiresEddie Hung2019-07-221-7/+13
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| * | | | | | | | | | | | | Indirection via $__soft_mulEddie Hung2019-07-192-9/+10
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| * | | | | | | | | | | | | Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5
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| * | | | | | | | | | | | | Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
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| * | | | | | | | | | | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
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| * | | | | | | | | | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
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| * | | | | | | | | | | | | Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
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| | * | | | | | | | | | | | | Fix typo in BEddie Hung2019-07-191-1/+1
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| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1815-84/+164
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| * | \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
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| * | | | | | | | | | | | | | | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
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| * | | | | | | | | | | | | | | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
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| * | | | | | | | | | | | | | | | Add paramsEddie Hung2019-07-181-0/+6
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| * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
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| * | | | | | | | | | | | | | | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
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| * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1814-51/+146
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| * | | | | | | | | | | | | | | | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
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| * | | | | | | | | | | | | | | | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
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| * | | | | | | | | | | | | | | | Make consistentEddie Hung2019-07-181-1/+2
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| * | | | | | | | | | | | | | | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
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| * | | | | | | | | | | | | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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| * | | | | | | | | | | | | | | | Working for unsignedEddie Hung2019-07-181-52/+28
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| * | | | | | | | | | | | | | | | CleanupEddie Hung2019-07-181-70/+58
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| * | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| | * | | | | | | | | | | | | | | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
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| * | | | | | | | | | | | | | | | | Make all operands signedEddie Hung2019-07-171-1/+1
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| * | | | | | | | | | | | | | | | | Update commentEddie Hung2019-07-171-5/+3
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| * | | | | | | | | | | | | | | | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
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| * | | | | | | | | | | | | | | | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
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| * | | | | | | | | | | | | | | | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
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| * | | | | | | | | | | | | | | | SignednessEddie Hung2019-07-162-8/+8
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| * | | | | | | | | | | | | | | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
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| * | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| | * | | | | | | | | | | | | | | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
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| | * | | | | | | | | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
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| | * | | | | | | | | | | | | | | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
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| | * | | | | | | | | | | | | | | | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
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| * | | | | | | | | | | | | | | | | Do not swap if equalsEddie Hung2019-07-151-1/+1
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| * | | | | | | | | | | | | | | | | Oops forgot these filesEddie Hung2019-07-152-0/+5
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| * | | | | | | | | | | | | | | | | OUT port to Y in generic DSPEddie Hung2019-07-152-3/+3
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| * | | | | | | | | | | | | | | | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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| * | | | | | | | | | | | | | | | Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
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| * | | | | | | | | | | | | | | | Tidy upEddie Hung2019-07-151-39/+26
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