| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | ecp5: Full set of IO-related blackboxes | David Shah | 2019-02-12 | 1 | -0/+102 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: Support for flipflop initialisation | David Shah | 2019-01-22 | 3 | -4/+199 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: Add LSRMODE to flipflops for PRLD support | David Shah | 2019-01-21 | 1 | -7/+16 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: More blackboxes | David Shah | 2019-01-21 | 1 | -0/+17 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | ecp5: Increase threshold for ALU mapping | David Shah | 2019-01-21 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module | Larry Doolittle | 2019-02-26 | 1 | -22/+22 | |
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| | * | | Clean up some whitepsace outliers | Larry Doolittle | 2019-02-26 | 1 | -2/+2 | |
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| * | | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 1 | -2/+2 | |
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| * | | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 | |
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| * | | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 | |
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| * | | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 | |
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| * | | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 2 | -18/+2 | |
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| * | | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
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| * | | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
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| * | | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 2 | -24/+29 | |
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| * | | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 2 | -22/+19 | |
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| * | | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
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| * | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
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| * | | Merge pull request #740 from daveshah1/improve_dress | Clifford Wolf | 2019-02-22 | 2 | -3/+3 | |
| |\ \ | | | | | | | Improve ABC netname preservation | |||||
| | * | | ecp5: Use abc -dress | David Shah | 2019-02-06 | 1 | -2/+2 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| | * | | ice40: Use abc -dress in synth_ice40 | David Shah | 2019-02-06 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | |||||
| * | | | Bugfix in ice40_dsp | Clifford Wolf | 2019-02-21 | 2 | -20/+33 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add ice40 test_dsp_map test case generator | Clifford Wolf | 2019-02-20 | 2 | -0/+99 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "synth_ice40 -dsp" | Clifford Wolf | 2019-02-20 | 1 | -3/+27 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Improve iCE40 SB_MAC16 model | Clifford Wolf | 2019-02-20 | 5 | -121/+179 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add first draft of functional SB_MAC16 model | Clifford Wolf | 2019-02-19 | 4 | -53/+467 | |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * / | Fixed Anlogic simulation model | Miodrag Milanovic | 2019-01-25 | 1 | -1/+1 | |
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| * | Add SF2 IO buffer insertion | Clifford Wolf | 2019-01-17 | 4 | -1/+168 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "synth_sf2 -vlog", fix "synth_sf2 -edif" | Clifford Wolf | 2019-01-17 | 1 | -2/+17 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #777 from mmicko/achronix_cell_sim_fix | Clifford Wolf | 2019-01-04 | 1 | -1/+1 | |
| |\ | | | | | Fix cells_sim.v for Achronix FPGA | |||||
| | * | Fix cells_sim.v for Achronix FPGA | Miodrag Milanovic | 2019-01-04 | 1 | -1/+1 | |
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| * | | Unify usage of noflatten among architectures | Miodrag Milanovic | 2019-01-04 | 4 | -8/+16 | |
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| * | Merge pull request #755 from Icenowy/anlogic-dram-init | Clifford Wolf | 2019-01-02 | 6 | -2/+96 | |
| |\ | | | | | anlogic: implement DRAM initialization | |||||
| | * | anlogic: implement DRAM initialization | Icenowy Zheng | 2018-12-20 | 6 | -2/+96 | |
| | | | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
| * | | Merge pull request #750 from Icenowy/anlogic-ff-init | Clifford Wolf | 2019-01-02 | 2 | -14/+15 | |
| |\ \ | | | | | | | Initialization of Anlogic DFFs | |||||
| | * | | anlogic: set the init value of DFFs | Icenowy Zheng | 2018-12-18 | 2 | -14/+15 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
| * | | | Merge pull request #772 from whitequark/synth_lut | Clifford Wolf | 2019-01-02 | 2 | -7/+41 | |
| |\ \ \ | | | | | | | | | synth: add k-LUT mode | |||||
| | * | | | synth_ice40: use 4-LUT coarse synthesis mode. | whitequark | 2019-01-02 | 1 | -1/+1 | |
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| | * | | | synth: add k-LUT mode. | whitequark | 2019-01-02 | 1 | -2/+36 | |
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| | * | | | synth: improve script documentation. NFC. | whitequark | 2019-01-02 | 1 | -6/+6 | |
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| * | | | | Merge pull request #771 from whitequark/techmap_cmp2lut | Clifford Wolf | 2019-01-02 | 2 | -1/+106 | |
| |\| | | | | | | | | | | | cmp2lut: new techmap pass | |||||
| | * | | | cmp2lut: new techmap pass. | whitequark | 2019-01-02 | 2 | -1/+106 | |
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| * | | | | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 15 | -22/+22 | |
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | | | Merge pull request #766 from Icenowy/anlogic-latches | Clifford Wolf | 2018-12-31 | 1 | -0/+12 | |
| |\ \ \ | | | | | | | | | anlogic: add latch cells | |||||
| | * | | | anlogic: add latch cells | Icenowy Zheng | 2018-12-25 | 1 | -0/+12 | |
| | | |/ | |/| | | | | | | | | | | | | | | | | Add latch cells to Anlogic cells replacement library by copying other FPGAs' latch code to it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
| * / | | Fix 7 instances of add_share_file to add_gen_share_file | Larry Doolittle | 2018-12-29 | 1 | -8/+8 | |
| |/ / | | | | | | | in techlibs/ecp5/Makefile.inc to permit out-of-tree builds | |||||
| * | | Merge pull request #752 from Icenowy/anlogic-lut-cost | Clifford Wolf | 2018-12-19 | 1 | -1/+1 | |
| |\ \ | | | | | | | Anlogic: let LUT5/6 have more cost than LUT4- | |||||
| | * | | Anlogic: let LUT5/6 have more cost than LUT4- | Icenowy Zheng | 2018-12-19 | 1 | -1/+1 | |
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
| * | | Merge pull request #753 from Icenowy/anlogic-makefile-fix | Clifford Wolf | 2018-12-19 | 1 | -0/+1 | |
| |\ \ | | | | | | | anlogic: fix Makefile.inc | |||||
| | * | | anlogic: fix Makefile.inc | Icenowy Zheng | 2018-12-19 | 1 | -0/+1 | |
| | |/ | | | | | | | | | | | | | | | | | During the addition of DRAM inferring support, the installation of eagle_bb.v is accidentally removed. Fix this issue. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> | |||||
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index : iCE40/yosys | |
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