| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Convert to use #945 | Eddie Hung | 2019-04-21 | 2 | -9/+3 |
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| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 2 | -10/+12 |
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| | * | Revert "synth_* with -retime option now calls abc with -D 1 as well" | Eddie Hung | 2019-04-18 | 11 | -15/+15 |
| | | | | | | | | | This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a. | ||||
| | * | Merge branch 'master' into eddie/fix_retime | Eddie Hung | 2019-04-18 | 4 | -44/+69 |
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| | * | | synth_* with -retime option now calls abc with -D 1 as well | Eddie Hung | 2019-04-10 | 11 | -15/+15 |
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| | * | | Move techamp t:$_DFF_?N? to before abc call | Eddie Hung | 2019-04-05 | 1 | -2/+2 |
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| | * | | Retry | Eddie Hung | 2019-04-05 | 1 | -1/+1 |
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| | * | | Resolve @daveshah1 comment, update synth_xilinx help | Eddie Hung | 2019-04-05 | 2 | -7/+9 |
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| | * | | synth_xilinx to techmap FFs after abc call, otherwise -retime fails | Eddie Hung | 2019-04-05 | 1 | -3/+3 |
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| * | | | ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set | Eddie Hung | 2019-04-19 | 2 | -4/+7 |
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| * | | | Make SB_DFF whitebox | Eddie Hung | 2019-04-19 | 3 | -3/+3 |
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| * | | | Fix SB_DFF comb model | Eddie Hung | 2019-04-18 | 2 | -3/+3 |
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| * | | | Missing close bracket | Eddie Hung | 2019-04-18 | 1 | -1/+1 |
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| * | | | Annotate SB_DFF* with abc_flop and abc_box_id | Eddie Hung | 2019-04-18 | 1 | -22/+49 |
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| * | | | Add SB_DFF* to boxes | Eddie Hung | 2019-04-18 | 3 | -6/+306 |
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| * | | | Use new -wb flag for ABC flow | Eddie Hung | 2019-04-18 | 3 | -19/+5 |
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| * | | | Also update Makefile.inc | Eddie Hung | 2019-04-18 | 1 | -7/+6 |
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| * | | | Make SB_LUT4 a blackbox | Eddie Hung | 2019-04-18 | 3 | -3/+3 |
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| * | | | Fix rename | Eddie Hung | 2019-04-18 | 1 | -0/+0 |
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| * | | | Rename to abc_*.{box,lut} | Eddie Hung | 2019-04-18 | 6 | -0/+0 |
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| * | | | Update Makefile.inc too | Eddie Hung | 2019-04-17 | 1 | -4/+6 |
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| * | | | Reduce to three devices: hx, lp, u | Eddie Hung | 2019-04-17 | 7 | -4/+23 |
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| * | | | Add up5k timings | Eddie Hung | 2019-04-17 | 2 | -0/+19 |
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| * | | | Fix grammar | Eddie Hung | 2019-04-17 | 1 | -2/+2 |
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| * | | | Update error message | Eddie Hung | 2019-04-17 | 1 | -1/+1 |
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| * | | | Add "-device" argument to synth_ice40 | Eddie Hung | 2019-04-17 | 4 | -7/+20 |
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| * | | | Missing abc_flop_q attribute on SPRAM | Eddie Hung | 2019-04-17 | 1 | -1/+1 |
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| * | | | Map to SB_LUT4 from fastest input first | Eddie Hung | 2019-04-17 | 1 | -7/+11 |
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| * | | | Mark seq output ports with "abc_flop_q" attr | Eddie Hung | 2019-04-17 | 1 | -24/+24 |
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| * | | | Also update Makefile.inc | Eddie Hung | 2019-04-17 | 1 | -3/+3 |
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| * | | | synth_ice40 to use renamed files | Eddie Hung | 2019-04-17 | 1 | -2/+2 |
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| * | | | Rename to abc.* | Eddie Hung | 2019-04-17 | 3 | -0/+0 |
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| * | | | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" | Eddie Hung | 2019-04-17 | 7 | -102/+35 |
| | | | | | | | | | | | | | This reverts commit a7632ab3326c5247b8152a53808413b259c13253. | ||||
| * | | | Try using an ICE40_CARRY_LUT primitive to avoid ABC issues | Eddie Hung | 2019-04-17 | 7 | -35/+102 |
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| * | | | Fix spacing | Eddie Hung | 2019-04-17 | 1 | -5/+5 |
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| * | | | Add SB_LUT4 to box library | Eddie Hung | 2019-04-16 | 3 | -0/+16 |
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| * | | | Add ice40 box files | Eddie Hung | 2019-04-16 | 6 | -1/+27 |
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| * | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-12 | 1 | -1/+9 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-12 | 4 | -44/+69 |
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| | * | | Merge pull request #928 from litghost/add_xc7_sim_models | Eddie Hung | 2019-04-12 | 3 | -41/+60 |
| | |\ \ | | | | | | | | | Add additional cells sim models for core 7-series primitives. | ||||
| | | * | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. | Keith Rothman | 2019-04-12 | 3 | -52/+14 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | * | | Fix LUT6_2 definition. | Keith Rothman | 2019-04-09 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | | * | | Add additional cells sim models for core 7-series primatives. | Keith Rothman | 2019-04-09 | 1 | -0/+57 |
| | | |/ | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| | * / | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 |
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| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 32 | -384/+1646 |
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| | * | xilinx: Add keep attribute where appropriate | David Shah | 2019-03-22 | 2 | -25/+31 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 | Clifford Wolf | 2019-03-19 | 1 | -2/+4 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes | Clifford Wolf | 2019-03-12 | 1 | -19/+0 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Fix typo in ice40_braminit help msg | Clifford Wolf | 2019-03-09 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge pull request #859 from smunaut/ice40_braminit | Clifford Wolf | 2019-03-09 | 4 | -37/+212 |
| | |\ | | | | | | | iCE40 BRAM primitives init from file | ||||
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index : iCE40/yosys | |
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