aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
...
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-211-4/+5
|\| | |
| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-4/+5
| |\| |
| | * | ecp5: Improve mapping of $alu when BI is usedDavid Shah2019-06-211-4/+5
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-201-1/+1
| |\| |
| * | | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
| | | |
* | | | Constrain wreduce only if wide muxEddie Hung2019-06-211-1/+4
| | | |
* | | | Simplify and comment out mux_map.vEddie Hung2019-06-211-6/+11
| | | |
* | | | synth_xilinx to now wreduce except $mux, remove extra peepoptEddie Hung2019-06-211-8/+1
| | | |
* | | | mux_map to no longer copy last value into 1'bxEddie Hung2019-06-211-19/+2
| | | |
* | | | Fix spacingEddie Hung2019-06-211-3/+3
| | | |
* | | | Fix spacing again, A_forward -> A_backwardEddie Hung2019-06-211-38/+40
| | | |
* | | | Restore wreduce to synth_xilinx, after muxcoverEddie Hung2019-06-211-0/+1
| | | |
* | | | Revert B_SIGNED optimisation, since only works for Y_WIDTH==1Eddie Hung2019-06-211-4/+3
| | | |
* | | | Fix spacingEddie Hung2019-06-211-15/+15
| | | |
* | | | synth_xilinx to use _ABC macro, and perform muxpack againEddie Hung2019-06-211-5/+5
| | | |
* | | | Add $__XILINX_MUXF78 to preserve entire boxEddie Hung2019-06-213-7/+28
| | | |
* | | | Fix alignmentEddie Hung2019-06-211-1/+1
| | | |
* | | | Add FIXME about need for -mux4Eddie Hung2019-06-211-0/+2
| | | |
* | | | Since muxcover uses MUX4s, blast them back to gates hereEddie Hung2019-06-211-0/+7
| | | |
* | | | Expand synth -coarse without wreduce, move muxcoverEddie Hung2019-06-211-12/+24
| | | |
* | | | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
| | | |
* | | | mux_map to drop sign bit, and eliminate 'bx-esEddie Hung2019-06-201-13/+47
| | | |
* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-201-1/+1
|\ \ \ \ | | |/ / | |/| |
| * | | Fixed small typo in ice40_unlut help summaryacw12512019-06-191-1/+1
| | | |
| * | | Fixed the help summary line for a few commandsacw12512019-06-191-1/+1
| | | |
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-181-29/+27
|\ \ \ \ | | |/ / | |/| |
| * | | Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
| | | |
| * | | Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
| | | | | | | | | | | | | | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d.
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-182-37/+37
|\| | |
| * | | Clean upEddie Hung2019-06-181-6/+4
| | | |
| * | | Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
| | | |
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-9/+8
|\| | |
| * | | Fix copy-pasta issueEddie Hung2019-06-171-9/+8
| | | |
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-172-33/+59
|\| | |
| * | | Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
| | | |
| * | | Simplify commentEddie Hung2019-06-171-1/+1
| | | |
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-5/+5
|\| | |
| * | | Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
| | | |
| * | | Try -W 300Eddie Hung2019-06-171-1/+2
| | | |
* | | | Try -W 300Eddie Hung2019-06-161-1/+2
| | | |
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-151-2/+2
|\| | |
| * | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
| | | |
* | | | Revert "Remove wide mux inference"Eddie Hung2019-06-144-3/+194
|/ / / | | | | | | | | | This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca.
* | | As per @daveshah1 remove async DFF timing from xilinxEddie Hung2019-06-141-2/+2
| | |
* | | Resolve comments from @daveshah1Eddie Hung2019-06-141-1/+1
| | |
* | | Add XC7_WIRE_DELAY macro to synth_xilinx.ccEddie Hung2019-06-141-1/+3
| | |
* | | Update delays based on SymbiFlow/prjxray-dbEddie Hung2019-06-141-12/+13
| | |
* | | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-144-3/+3
| | |
* | | Comment out dist RAM boxing on ECP5 for nowEddie Hung2019-06-141-1/+1
| | |
* | | Remove WIP ABC9 flop supportEddie Hung2019-06-144-46/+46
| | |