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| * | | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
| |\ \ \ | | |/ / | |/| | ECP5 Improvements
| | * | ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | ecp5: More blackboxesDavid Shah2019-01-211-0/+17
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | ecp5: Increase threshold for ALU mappingDavid Shah2019-01-211-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-264-27/+27
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| * | | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut moduleLarry Doolittle2019-02-261-22/+22
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| * | | Clean up some whitepsace outliersLarry Doolittle2019-02-261-2/+2
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| * | Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-222-3/+3
| |\ \ | | | | | | | | Improve ABC netname preservation
| | * | ecp5: Use abc -dressDavid Shah2019-02-061-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * | ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-216-58/+667
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| * | | Bugfix in ice40_dspClifford Wolf2019-02-212-20/+33
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | synth to take -abc9 argumentEddie Hung2019-02-201-5/+13
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* | | Merge branch 'master' into xaigEddie Hung2019-02-192-86/+43
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* | | synth_ice40 to have new -abc9 argEddie Hung2019-02-141-4/+12
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* | | Cope WIDTH of ff/latch cells is default of zeroEddie Hung2019-02-061-6/+6
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* | | Add INIT parameter to all ff/latch cellsEddie Hung2019-02-062-43/+86
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* / Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
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* Add SF2 IO buffer insertionClifford Wolf2019-01-174-1/+168
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
|\ | | | | Fix cells_sim.v for Achronix FPGA
| * Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
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* | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\ | | | | anlogic: implement DRAM initialization
| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
| | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
|\ \ | | | | | | Initialization of Anlogic DFFs
| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
|\ \ \ | | | | | | | | synth: add k-LUT mode
| * | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
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| * | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
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| * | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
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* | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
|\| | | | | | | | | | | cmp2lut: new techmap pass
| * | | cmp2lut: new techmap pass.whitequark2019-01-022-1/+106
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* | | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0215-22/+22
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* | | Merge pull request #766 from Icenowy/anlogic-latchesClifford Wolf2018-12-311-0/+12
|\ \ \ | | | | | | | | anlogic: add latch cells
| * | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
| | |/ | |/| | | | | | | | | | | | | | | | Add latch cells to Anlogic cells replacement library by copying other FPGAs' latch code to it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* / | Fix 7 instances of add_share_file to add_gen_share_fileLarry Doolittle2018-12-291-8/+8
|/ / | | | | | | in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
* | Merge pull request #752 from Icenowy/anlogic-lut-costClifford Wolf2018-12-191-1/+1
|\ \ | | | | | | Anlogic: let LUT5/6 have more cost than LUT4-
| * | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #753 from Icenowy/anlogic-makefile-fixClifford Wolf2018-12-191-0/+1
|\ \ | | | | | | anlogic: fix Makefile.inc
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