| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 5 | -279/+211 | |
| | | | | | | | | | * remove unused techmap models in `map_regs.v` * replace RAM initilization loops with 320-bit-writes * add script to test targets in top-level Makefile * remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v` * iterate over all modules in `gatemate_bramopt` pass | |||||
| * | synth_gatemate: Apply review remarks | Patrick Urban | 2021-11-13 | 5 | -141/+86 | |
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| * | synth_gatemate: Initial implementation | Patrick Urban | 2021-11-13 | 15 | -0/+3716 | |
| | | | | | Signed-off-by: Patrick Urban <patrick.urban@web.de> | |||||
| * | iopadmap: Add native support for negative-polarity output enable. | Marcelina Kościelnicka | 2021-11-09 | 9 | -33/+10 | |
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| * | synth_gowin: move splitnets to after iopadmap (#2435) | Pepijn de Vos | 2021-11-07 | 1 | -2/+3 | |
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| * | Remove noalu from synth_gowin json output as Apicula now supports it | Pepijn de Vos | 2021-11-07 | 1 | -1/+0 | |
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| * | gowin: widelut support (#3042) | Pepijn de Vos | 2021-11-06 | 1 | -1/+0 | |
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| * | ecp5: Add support for mapping aldff. | Marcelina Kościelnicka | 2021-10-27 | 2 | -13/+13 | |
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| * | Fixed Verific parser error in ice40 cell library | Claire Xenia Wolf | 2021-10-19 | 1 | -22/+62 | |
| | | | | | non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode | |||||
| * | CycloneV: Add (passthrough) support for cyclonev_oscillator | Olivier Galibert | 2021-10-17 | 1 | -1/+11 | |
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| * | CycloneV: Add (passthrough) support for ↵ | Olivier Galibert | 2021-10-17 | 1 | -0/+8 | |
| | | | | | cyclonev_hps_interface_mpu_general_purpose | |||||
| * | Hook up $aldff support in various passes. | Marcelina Kościelnicka | 2021-10-02 | 1 | -1/+1 | |
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| * | Add $aldff and $aldffe: flip-flops with async load. | Marcelina Kościelnicka | 2021-10-02 | 3 | -0/+382 | |
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| * | abc9: replace cell type/parameters if derived type already processed (#2991) | Eddie Hung | 2021-09-09 | 1 | -1/+1 | |
| | | | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review | |||||
| * | [ECP5] fix wrong link for syn_* attributes description (#2984) | kittennbfive | 2021-08-29 | 2 | -2/+2 | |
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| * | Add DLLDELD | ECP5-PCIe | 2021-08-22 | 1 | -0/+9 | |
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| * | Gowin: deal with active-low tristate (#2971) | Pepijn de Vos | 2021-08-20 | 4 | -6/+13 | |
| | | | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests | |||||
| * | ice40: Fix typo in SB_CARRY specify for LP/UltraPlus | Sylvain Munaut | 2021-08-17 | 1 | -2/+2 | |
| | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 1 | -0/+169 | |
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| * | Fixes xc7 BRAM36s | Maciej Dudek | 2021-07-30 | 1 | -4/+6 | |
| | | | | | | | UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode. Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | |||||
| * | opt_lut: Allow more than one -dlogic per cell type. | Marcelina Kościelnicka | 2021-07-29 | 1 | -1/+1 | |
| | | | | | Fixes #2061. | |||||
| * | memory: Introduce $meminit_v2 cell, with EN input. | Marcelina Kościelnicka | 2021-07-28 | 1 | -0/+24 | |
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| * | ice40: Fix LUT input indices in opt_lut -dlogic (again). | Marcelina Kościelnicka | 2021-07-10 | 1 | -1/+1 | |
| | | | | | Fixes #2061. | |||||
| * | ecp5: Add DCSC blackbox | gatecat | 2021-07-06 | 1 | -0/+10 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | Fix icestorm links | Claire Xenia Wolf | 2021-06-09 | 2 | -516/+516 | |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | Use HTTPS for website links, gatecat email | Claire Xenia Wolf | 2021-06-09 | 6 | -6/+6 | |
| | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g; | |||||
| * | Fix files with CRLF line endings | Claire Xenia Wolf | 2021-06-09 | 2 | -349/+349 | |
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| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 58 | -64/+64 | |
| | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | |||||
| * | intel_alm: Fix illegal carry chains | gatecat | 2021-05-15 | 2 | -3/+5 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | intel_alm: Add global buffer insertion | gatecat | 2021-05-15 | 6 | -4/+78 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | intel_alm: Add IO buffer insertion | gatecat | 2021-05-15 | 6 | -7/+127 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib. | Adam Greig | 2021-05-12 | 1 | -0/+22 | |
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| * | Fix use of blif name in synth_xilinx command | Michael Christensen | 2021-04-27 | 1 | -1/+1 | |
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| * | Add default assignments to other SB_* simulation models | Claire Xenia Wolf | 2021-04-20 | 1 | -24/+44 | |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | Add default assignments to SB_LUT4 | Claire Xenia Wolf | 2021-04-20 | 1 | -1/+17 | |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | quicklogic: ABC9 synthesis | Lofty | 2021-04-17 | 6 | -5/+80 | |
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| * | sf2: fix name of AND modules | Stefan Riesenberger | 2021-04-09 | 1 | -3/+3 | |
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| * | abc9: fix SCC issues (#2694) | Eddie Hung | 2021-03-29 | 2 | -0/+9 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review | |||||
| * | quicklogic: PolarPro 3 support | Lofty | 2021-03-18 | 9 | -0/+770 | |
| | | | | | | | | | Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com> | |||||
| * | Blackbox all whiteboxes after synthesis | gatecat | 2021-03-17 | 15 | -0/+15 | |
| | | | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | memory_dff: Remove now-useless write port handling. | Marcelina Kościelnicka | 2021-03-08 | 1 | -6/+7 | |
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| * | Fix syntax error in adff2dff.v | Marcelina Kościelnicka | 2021-02-24 | 1 | -1/+1 | |
| | | | | | Fixes #2600. | |||||
| * | machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ↵ | William D. Jones | 2021-02-23 | 1 | -11/+5 | |
| | | | | | values. | |||||
| * | machxo2: Add experimental status to help. | William D. Jones | 2021-02-23 | 1 | -1/+1 | |
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| * | machxo2: Add DCCA and DCMA blackbox primitives. | William D. Jones | 2021-02-23 | 1 | -0/+17 | |
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| * | machxo2: Fix reversed interpretation of REG_SD config bits. | William D. Jones | 2021-02-23 | 1 | -2/+2 | |
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| * | machxo2: Tristate is active-low. | William D. Jones | 2021-02-23 | 2 | -5/+5 | |
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| * | machxo2: Fix typos in FACADE_FF sim model. | William D. Jones | 2021-02-23 | 1 | -5/+4 | |
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| * | machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. | William D. Jones | 2021-02-23 | 2 | -6/+6 | |
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| * | machxo2: Improve help_mode output in synth_machxo2. | William D. Jones | 2021-02-23 | 1 | -5/+5 | |
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index : iCE40/yosys | |
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