| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | synth_intel: s/not family/no family/ | Dan Ravensloft | 2019-07-18 | 1 | -2/+2 | |
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| | | * | | | intel_synth: Fix help message | Ben Widawsky | 2019-07-18 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
| | | * | | | intel_synth: Small code cleanup to remove if ladder | Ben Widawsky | 2019-07-18 | 1 | -28/+10 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
| | | * | | | intel_synth: Make family explicit and match | Ben Widawsky | 2019-07-18 | 1 | -2/+6 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
| | | * | | | intel_synth: Minor code cleanups | Ben Widawsky | 2019-07-18 | 1 | -2/+6 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
| | * | | | | synth_intel: rename for consistency with #1184 | Dan Ravensloft | 2019-07-18 | 1 | -4/+4 | |
| | |/ / / | | | | | | | | | | | | | Also fix a typo in the help message. | |||||
| * | | | | Do not define `DSP_SIGNEDONLY macro if no exists | Eddie Hung | 2019-07-18 | 1 | -4/+3 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 14 | -51/+146 | |
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| | * | | | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 5 | -17/+21 | |
| | |\ \ \ | | | | | | | | | | | synth_{ice40,ecp5}: more sensible pass label naming | |||||
| | | * | | | synth_ecp5: rename dram to lutram everywhere. | whitequark | 2019-07-16 | 4 | -13/+13 | |
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| | | * | | | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 2 | -5/+9 | |
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| | * | | | | Merge pull request #1204 from smunaut/fix_1187 | David Shah | 2019-07-17 | 2 | -4/+4 | |
| | |\ \ \ \ | | | | | | | | | | | | | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map | |||||
| | | * | | | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map | Sylvain Munaut | 2019-07-16 | 2 | -4/+4 | |
| | | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| | * / | | | gen_lut to return correctly sized LUT mask | Eddie Hung | 2019-07-16 | 1 | -1/+1 | |
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| | * | | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix | Eddie Hung | 2019-07-16 | 8 | -29/+120 | |
| | |\ \ \ | | |/ / | |/| | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box | |||||
| | | * | | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark | Eddie Hung | 2019-07-15 | 7 | -8/+8 | |
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| | | * | | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT | Eddie Hung | 2019-07-13 | 1 | -9/+7 | |
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| | | * | | Use Const::from_string() not its constructor... | Eddie Hung | 2019-07-12 | 1 | -1/+1 | |
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| | | * | | Off by one | Eddie Hung | 2019-07-12 | 1 | -1/+1 | |
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| | | * | | Fix spacing | Eddie Hung | 2019-07-12 | 1 | -1/+1 | |
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| | | * | | Remove double push | Eddie Hung | 2019-07-12 | 1 | -1/+0 | |
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| | | * | | Map to and from this box if -abc9 | Eddie Hung | 2019-07-12 | 1 | -2/+3 | |
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| | | * | | ice40_opt to handle this box and opt back to SB_LUT4 | Eddie Hung | 2019-07-12 | 1 | -0/+48 | |
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| | | * | | Add new box to cells_sim.v | Eddie Hung | 2019-07-12 | 1 | -2/+25 | |
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| | | * | | _ABC macro will map and unmap to this new box | Eddie Hung | 2019-07-12 | 2 | -0/+34 | |
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| | | * | | Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box | Eddie Hung | 2019-07-12 | 3 | -25/+13 | |
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| * | | | | synth_ice40 to decompose into 16x16 | Eddie Hung | 2019-07-18 | 1 | -1/+3 | |
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| * | | | | mul2dsp to create cells that can be interchanged with $mul | Eddie Hung | 2019-07-18 | 1 | -1/+7 | |
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| * | | | Make consistent | Eddie Hung | 2019-07-18 | 1 | -1/+2 | |
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| * | | | Fix signed multiplier decomposition | Eddie Hung | 2019-07-18 | 1 | -29/+36 | |
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| * | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 | |
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| * | | | Working for unsigned | Eddie Hung | 2019-07-18 | 1 | -52/+28 | |
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| * | | | Cleanup | Eddie Hung | 2019-07-18 | 1 | -70/+58 | |
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| * | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-18 | 1 | -31/+41 | |
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| | * | | | mul2dsp: Lower partial products always have unsigned inputs | David Shah | 2019-07-18 | 1 | -31/+41 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | Make all operands signed | Eddie Hung | 2019-07-17 | 1 | -1/+1 | |
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| * | | | | Update comment | Eddie Hung | 2019-07-17 | 1 | -5/+3 | |
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| * | | | Fix mul2dsp signedness | Eddie Hung | 2019-07-17 | 1 | -42/+38 | |
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| * | | | A_SIGNED == B_SIGNED so flip both | Eddie Hung | 2019-07-17 | 1 | -21/+12 | |
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| * | | | Add DSP_{A,B}_SIGNEDONLY macro | Eddie Hung | 2019-07-16 | 1 | -11/+40 | |
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| * | | | Signedness | Eddie Hung | 2019-07-16 | 2 | -8/+8 | |
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| * | | | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 2 | -4/+4 | |
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| * | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 4 | -27/+35 | |
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| | * | | | xilinx: Add correct signed behaviour to DSP48E1 model | David Shah | 2019-07-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵ | David Shah | 2019-07-16 | 2 | -4/+8 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH | David Shah | 2019-07-16 | 1 | -18/+22 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | mul2dsp: Fix indentation | David Shah | 2019-07-16 | 1 | -7/+7 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | Add support for {A,B,P}REG in DSP48E1 | Eddie Hung | 2019-07-16 | 1 | -5/+21 | |
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| * | | | | Do not swap if equals | Eddie Hung | 2019-07-15 | 1 | -1/+1 | |
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| * | | | | Oops forgot these files | Eddie Hung | 2019-07-15 | 2 | -0/+5 | |
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index : iCE40/yosys | |
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