aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
...
| * | | | | | | | | | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
| | | | | | | | | | | | | |
| * | | | | | | | | | | | | Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
| |\ \ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | | Fix typo in BEddie Hung2019-07-191-1/+1
| | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1815-84/+164
| | |\ \ \ \ \ \ \ \ \ \ \ \ \
| * | \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Add paramsEddie Hung2019-07-181-0/+6
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / / / / / / | | |/| | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1814-51/+146
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
| | |_|_|/ / / / / / / / / / / / / | |/| | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Make consistentEddie Hung2019-07-181-1/+2
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Working for unsignedEddie Hung2019-07-181-52/+28
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | CleanupEddie Hung2019-07-181-70/+58
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | | | | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | Make all operands signedEddie Hung2019-07-171-1/+1
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | Update commentEddie Hung2019-07-171-5/+3
| |/ / / / / / / / / / / / / / / /
| * | | | | | | | | | | | | | | | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | SignednessEddie Hung2019-07-162-8/+8
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | | | | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | | | | | | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | | | | | | | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | Do not swap if equalsEddie Hung2019-07-151-1/+1
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | Oops forgot these filesEddie Hung2019-07-152-0/+5
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | OUT port to Y in generic DSPEddie Hung2019-07-152-3/+3
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
| |/ / / / / / / / / / / / / / / /
| * | | | | | | | | | | | | | | | Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Tidy upEddie Hung2019-07-151-39/+26
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
| | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1512-25/+609
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-104-45/+42
| | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-105-102/+193
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | | | xc7: Map combinational DSP48E1sDavid Shah2019-07-084-7/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | mul2dsp: Fix typoDavid Shah2019-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-085-2/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | Fix box nameEddie Hung2019-09-271-1/+1
| | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | Missing an '&'Eddie Hung2019-09-261-1/+1
| |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / |/| | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-198-90/+502
| |_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / |/| | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | Merge pull request #1379 from mmicko/sim_modelsEddie Hung2019-09-182-7/+162
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added simulation models for Efinix and Anlogic