iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	1	-6/+4
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*	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	1	-6/+0
\| \| \| \|	This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	1	-0/+6
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*	intel_alm: add Cyclone 10 GX tests	Dan Ravensloft	2020-07-05	11	-2/+236
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*	intel_alm: DSP inference	Dan Ravensloft	2020-07-05	1	-0/+23
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*	synth_intel_alm: Use dfflegalize.	Marcelina Kościelnicka	2020-07-04	1	-1/+1
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*	Improve MISTRAL_FF specify rules	Dan Ravensloft	2020-07-04	1	-1/+2
\| \| \| \|	Co-authored-by: Eddie Hung <eddie@fpgeh.com>
*	tests: update fsm.ys resource count	Eddie Hung	2020-07-04	1	-4/+4
\| \| \| \| \|	Suspect it is to do with map/set ordering in techmap; should be fixed by #1862?
*	intel_alm: fix DFFE matching	Dan Ravensloft	2020-06-11	2	-4/+4
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*	Add missing .gitignore file	Claire Wolf	2020-06-04	1	-0/+2
\| \| \| \|	Signed-off-by: Claire Wolf <claire@symbioticeda.com>
*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	1	-0/+20
\| \| \| \| \| \| \| \| \| \|	By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
*	intel_alm: work around a Quartus ICE	Dan Ravensloft	2020-04-23	1	-0/+12
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	10	-0/+208
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).