| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Merge pull request #1603 from whitequark/ice40-ram_style | whitequark | 2020-04-10 | 5 | -35/+551 | |
| |\ | | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes | |||||
| | * | ecp5: do not map FFRAM if explicitly requested otherwise. | whitequark | 2020-04-03 | 1 | -16/+62 | |
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| | * | ice40: do not map FFRAM if explicitly requested otherwise. | whitequark | 2020-04-03 | 1 | -8/+28 | |
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| | * | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. | whitequark | 2020-02-06 | 3 | -5/+305 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires). | |||||
| | * | ice40: match memory inference attribute values case insensitive. | whitequark | 2020-02-06 | 1 | -0/+6 | |
| | | | | | | | | | LSE/Synplify use case insensitive matching. | |||||
| | * | ice40: add support for both 1364.1 and LSE RAM/ROM attributes. | whitequark | 2020-02-06 | 3 | -20/+179 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires). | |||||
| | * | ice40: remove impossible test. | whitequark | 2020-02-06 | 1 | -15/+0 | |
| | | | | | | | | | | | | | iCE40 does not have LUTRAM. This was erroneously added in commit caab66111e2b5052bd26c8fd64b1324e7e4a4106, and tested for BRAM, essentially a duplicate of the "dpram.ys" test. | |||||
| * | | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor | Eddie Hung | 2020-04-01 | 2 | -7/+3 | |
| |\ \ | | | | | | | opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs | |||||
| | * | | Simplify breaking tests/arch/*/fsm.ys tests | Eddie Hung | 2020-03-20 | 2 | -7/+3 | |
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| * | | | fix argument order for macOS compatibility | N. Engelhardt | 2020-03-18 | 1 | -3/+3 | |
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| * | | tests: extend tests/arch/run-tests.sh for defines | Eddie Hung | 2020-03-05 | 1 | -3/+14 | |
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| * | | Merge pull request #1718 from boqwxp/precise_locations | Claire Wolf | 2020-03-03 | 1 | -2/+2 | |
| |\ \ | | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. | |||||
| | * | | Change attribute search value to specify precise location instead of simple ↵ | Alberto Gonzalez | 2020-02-24 | 1 | -2/+2 | |
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| * | | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" | Eddie Hung | 2020-02-27 | 1 | -3/+9 | |
| | | | | | | | | | | | | | This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5. | |||||
| * | | | Cleanup tests | Eddie Hung | 2020-02-27 | 1 | -0/+18 | |
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| * | | | Update bug1630.ys to use -lut 4 instead of lut file | Eddie Hung | 2020-02-27 | 1 | -1/+1 | |
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| * | | | Fix tests/arch/xilinx/fsm.ys to count flops only | Eddie Hung | 2020-02-27 | 1 | -9/+3 | |
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| * | | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 1 | -0/+20 | |
| | | | | | | | | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549 | |||||
| * | | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 3 | -1/+83 | |
| |/ | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547 | |||||
| * | Merge pull request #1650 from YosysHQ/eddie/shiftx2mux | Eddie Hung | 2020-02-05 | 2 | -5/+5 | |
| |\ | | | | | techmap LSB-first for compatible $shift/$shiftx cells | |||||
| | * | Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux | Eddie Hung | 2020-02-05 | 7 | -28/+173 | |
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| | * | | Update tests with reduced area | Eddie Hung | 2020-01-21 | 2 | -6/+6 | |
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| * | | | abc9_ops: -reintegrate to use derived_type for box_ports | Eddie Hung | 2020-02-05 | 1 | -1/+21 | |
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| * | | Add opt_lut_ins pass. (#1673) | Marcelina Kościelnicka | 2020-02-03 | 3 | -4/+61 | |
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| * | | Merge pull request #1559 from YosysHQ/efinix_test_fix | Miodrag Milanović | 2020-01-29 | 1 | -1/+1 | |
| |\ \ | | | | | | | Fix for non-deterministic test | |||||
| | * | | Updated test to use assert-max | Miodrag Milanovic | 2020-01-28 | 1 | -1/+1 | |
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| | * | | Fix for non-deterministic test | Miodrag Milanovic | 2019-12-07 | 1 | -1/+1 | |
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| * | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts | Eddie Hung | 2020-01-28 | 2 | -0/+102 | |
| |\ \ \ | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx | |||||
| | * | | | Import tests from #1628 | Eddie Hung | 2020-01-27 | 2 | -0/+102 | |
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| * | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate | N. Engelhardt | 2020-01-28 | 1 | -0/+5 | |
| |\ \ \ \ | |/ / / |/| | | | synth_xilinx: error out if tristate without '-iopad' | |||||
| | * | | | Add test | Eddie Hung | 2019-12-12 | 1 | -0/+5 | |
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| * | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 | Eddie Hung | 2020-01-24 | 1 | -23/+4 | |
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| * | | | xilinx_dsp: another typo; move xilinx specific test | Eddie Hung | 2020-01-17 | 1 | -0/+11 | |
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| * | | | ice40_dsp: fix typo | Eddie Hung | 2020-01-17 | 1 | -0/+11 | |
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| * | | | Add #1644 testcase | Eddie Hung | 2020-01-17 | 2 | -0/+2 | |
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| * | | | ice40_dsp: add test | Eddie Hung | 2020-01-17 | 1 | -0/+11 | |
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| * | | | Merge pull request #1632 from YosysHQ/eddie/fix1630 | Eddie Hung | 2020-01-14 | 2 | -0/+2 | |
| |\ \ \ | | | | | | | | | read_aiger: uniquify wires with $aiger<autoidx> prefix | |||||
| | * | | | Add #1630 testcase | Eddie Hung | 2020-01-13 | 2 | -0/+2 | |
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| * | | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attr | Miodrag Milanović | 2020-01-14 | 3 | -9/+8 | |
| |\ \ \ \ | |/ / / |/| | | | Export wire properties in EDIF | |||||
| | * | | | this one is fine | Miodrag Milanovic | 2020-01-10 | 1 | -3/+3 | |
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| | * | | | Fix tests | Miodrag Milanovic | 2020-01-10 | 3 | -12/+11 | |
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| * | | | | Add #1626 testcase | Eddie Hung | 2020-01-12 | 1 | -0/+217 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs | Eddie Hung | 2020-01-07 | 2 | -0/+123 | |
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| | * | | | Combine tests to check multiple clock domains | Eddie Hung | 2020-01-02 | 1 | -33/+10 | |
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| | * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 10 | -11/+31 | |
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| | * | | | | Add some abc9 dff tests | Eddie Hung | 2019-12-31 | 1 | -0/+55 | |
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| | * | | | | Add -D DFF_MODE to abc9_map test | Eddie Hung | 2019-12-30 | 1 | -4/+4 | |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-30 | 24 | -57/+224 | |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 20 | -66/+750 | |
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| | * \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 3 | -23/+136 | |
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index : iCE40/yosys | |
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