| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵ | Udi Finkelstein | 2018-10-25 | 1 | -0/+4 |
| parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages. | |||||
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index : iCE40/yosys | |
| [no description] |
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