| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. | whitequark | 2019-01-02 | 1 | -8/+14 | |
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| * | opt_expr: simplify any unsigned comparisons with all-0 and all-1. | whitequark | 2019-01-02 | 2 | -0/+15 | |
| | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input. | |||||
| * | opt_lut: eliminate LUTs evaluating to constants or inputs. | whitequark | 2018-12-31 | 3 | -0/+23 | |
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| * | Merge pull request #724 from whitequark/equiv_opt | Clifford Wolf | 2018-12-16 | 2 | -15/+1 | |
| |\ | | | | | equiv_opt: new command, for verifying optimization passes | |||||
| | * | equiv_opt: pass -D EQUIV when techmapping. | whitequark | 2018-12-07 | 2 | -4/+1 | |
| | | | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models. | |||||
| | * | equiv_opt: new command, for verifying optimization passes. | whitequark | 2018-12-07 | 1 | -12/+1 | |
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| * | | opt_lut: leave intact LUTs with cascade feeding module outputs. | whitequark | 2018-12-07 | 2 | -0/+20 | |
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| * | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 1 | -1/+1 | |
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| * | opt_lut: new pass, to combine LUTs for tighter packing. | whitequark | 2018-12-05 | 5 | -0/+43 | |
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index : iCE40/yosys | |
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