| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix tests/simple/specify.v | Clifford Wolf | 2018-03-27 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 1 | -0/+31 |
| The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST | |||||
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index : iCE40/yosys | |
| [no description] |
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