iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	verific: Fix conditions of SVAs with explicit clocks within procedures	Jannis Harder	2022-05-03	1	-0/+11
	For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case.