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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+41
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* dfflibmap: Refactor to use dfflegalize internally.Marcelina Kościelnicka2020-07-093-0/+135
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* clkbufmap: improve input pad handling.Marcelina Kościelnicka2020-07-091-0/+79
| | | | | | - allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
* clk2fflogic: Consistently treat async control signals as negative hold.Marcelina Kościelnicka2020-07-097-31/+31
| | | | | | | This fixes some dfflegalize equivalence checks, and breaks others — and I strongly suspect the others are due to bad support for multiple async inputs in `proc` (in particular, lack of proper support for dlatchsr and sketchy circuits on dffsr control inputs).
* dfflegalize: Add special support for const-D latches.Marcelina Kościelnicka2020-07-091-0/+53
| | | | | | Those can be created by `opt_dff` when optimizing `$adff` with const clock, or with D == Q. Make dfflegalize do the opposite transform when such dlatches would be otherwise unimplementable.
* dfflegalize: Add tests.Marcelina Kościelnicka2020-07-0117-0/+2957
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-232-76/+76
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* tests: zinit for new typesEddie Hung2020-04-141-2/+96
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* dffinit: Avoid setting init parameter to zero-length value.Marcelina Kościelnicka2020-04-141-0/+25
| | | | Fixes #1704.
* zinit: resolve one more comment by @mwkmwkmwkEddie Hung2020-04-131-1/+8
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* zinit: fix review comments from @mwkmwkmwkEddie Hung2020-04-131-4/+31
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* tests: zinit on $adffEddie Hung2020-04-131-19/+18
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* Add testcase for $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+24
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* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-0/+52
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-3/+31
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| * Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-1/+1
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| * techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-031-0/+24
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* | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+9
|/ | | | Fixes #1841.
* techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-0/+18
| | | | Fixes #1804.
* iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-021-2/+21
| | | | | iopadmap: Look harder for already-present buffers. Fixes #1720.
* Fine tune #1699 testsEddie Hung2020-02-131-14/+14
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* iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-131-0/+37
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* shiftx2mux: fix select out of boundsEddie Hung2020-02-052-1/+12
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* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-051-0/+29
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| * Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-0/+13
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| * | abc9: respect (* keep *) on cellsEddie Hung2020-01-131-0/+15
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| * | write_xaiger: add support and test for (* keep *) on wiresEddie Hung2020-01-131-0/+13
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* | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-211-4/+4
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* | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-211-0/+110
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* | abc9: aAdd test to check $_NOT_s are absorbedEddie Hung2020-01-151-0/+12
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* Add abc9 sanity testEddie Hung2020-01-091-0/+40
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* iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-251-0/+23
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* iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-0/+99
| | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not).
* clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-5/+16
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* Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-0/+10
|\ | | | | Add -select option to aigmap
| * Add quick testEddie Hung2019-09-301-0/+10
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* | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
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* | Add testEddie Hung2019-09-301-0/+16
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* Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-2/+12
| | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396.
* Hell let's add the original #1381 testcase tooEddie Hung2019-09-201-3/+22
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* Add testcaseEddie Hung2019-09-201-0/+43
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* Added extractinv passMarcin Kościelnicki2019-09-191-0/+41
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* Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-111-0/+50
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* techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-0/+98
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* improve clkbuf_inhibit propagation upwards through hierarchyMarcin Kościelnicki2019-08-271-5/+33
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* Improve tests to check that clkbuf is connected to expectedEddie Hung2019-08-261-6/+21
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* Check clkbuf_inhibit=1 is ignored for custom selectionEddie Hung2019-08-231-0/+1
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* Add simple clkbufmap testsEddie Hung2019-08-231-0/+52
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* tests/techmap/run-test.sh to cope with *.ysEddie Hung2019-08-232-7/+18
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* Add testEddie Hung2019-08-203-0/+15
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