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* Added tests for attributesMaciej Kurc2019-06-039-0/+219
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
|\ | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| * Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-282-33/+36
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'master' into wandworStefan Biereigel2019-05-272-0/+76
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| * Fix initEddie Hung2019-05-241-27/+27
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| * Fix typosEddie Hung2019-05-241-6/+6
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| * Add more testsEddie Hung2019-05-242-20/+41
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| * Call procEddie Hung2019-05-241-1/+1
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| * Fix duplicate driverEddie Hung2019-05-241-15/+15
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| * Add opt_rmdff testsEddie Hung2019-05-232-0/+55
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* | reformat wand/wor testStefan Biereigel2019-05-271-22/+21
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* | remove port direction workaround from test caseStefan Biereigel2019-05-271-2/+1
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* | add simple test case for wand/worStefan Biereigel2019-05-231-0/+35
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* Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Add test case from #997Clifford Wolf2019-05-071-0/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-0/+86
|\ | | | | Add specify parser
| * Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * More testingEddie Hung2019-05-032-2/+5
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| * Fix spacingEddie Hung2019-05-031-6/+6
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| * Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
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* | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-0/+25
|\ \ | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| * | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-066-5/+60
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| * | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-061-0/+52
|\ \ \ | |_|/ |/| | Improve verific -chparam and add hierarchy -chparam
| * | Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
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* | | Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+9
|\ \ \ | |/ / |/| | Improve pmgen, Add "peepopt" pass with shift-mul pattern
| * | Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-301-0/+9
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
|\ \ | | | | | | Fix width detection of memory access with bit slice
| * | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
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* | Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-012-0/+23
|/ | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
* Updaye pmux2shiftx testClifford Wolf2019-04-221-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #909 from zachjs/masterClifford Wolf2019-04-222-0/+48
|\ | | | | support repeat loops with constant repeat counts outside of constant functions
| * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-092-0/+48
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* | Merge pull request #944 from YosysHQ/clifford/pmux2shiftxClifford Wolf2019-04-222-0/+62
|\ \ | | | | | | Add pmux2shiftx command
| * | Improve "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in pmux2shiftxClifford Wolf2019-04-202-20/+30
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add test for pmux2shiftxClifford Wolf2019-04-202-0/+52
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix testsClifford Wolf2019-04-212-2/+3
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add tests/aiger/.gitignoreClifford Wolf2019-04-191-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add retime testEddie Hung2019-04-051-0/+6
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* Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
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* Liberty file parser now accepts superfluous ;Niels Moseley2019-03-273-2/+97
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* Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-0/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Updated the liberty parser to accept [A:B] ranges (AST has not been ↵Niels Moseley2019-03-246-0/+541
| | | | updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-1911-31/+175
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