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* | | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-0/+19
|/ / | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-052-7/+28
| | | | | | | | | | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* | Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+26
|/ | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-0423-6/+495
|\ | | | | verilog: significant block scoping improvements
| * verilog: significant block scoping improvementsZachary Snow2021-01-3123-6/+495
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | Merge pull request #2436 from dalance/fix_generatewhitequark2021-02-032-7/+4
|\ \ | | | | | | Fix begin/end in generate
| * | Fix begin/end in generatedalance2020-11-112-7/+4
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* | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-0/+20
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* | xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-272-1/+48
| | | | | | | | | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* | Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-251-0/+28
|\ \ | | | | | | verilog: allow spaces in macro arguments
| * | verilog: allow spaces in macro argumentsZachary Snow2021-01-201-0/+28
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* | | Allow combination of rand and const modifiersZachary Snow2021-01-212-0/+9
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* | | sv: fix support wire and var data type modifiersZachary Snow2021-01-202-0/+42
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* | Merge pull request #2547 from zachjs/plugin-so-dsymwhitequark2021-01-181-0/+1
|\ \ | | | | | | Add plugin.so.dSYM to .gitignore
| * | Add plugin.so.dSYM to .gitignoreZachary Snow2021-01-181-0/+1
| | | | | | | | | | | | | | | This artifact is automatically generated by the builtin clang on macOS when -g is used.
* | | Add typedef input/output testKamil Rakoczy2021-01-182-0/+117
|/ / | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | opt_share: Fix X and CO signal width for shifted $alu in opt_share.Marcelina Kościelnicka2021-01-141-0/+20
| | | | | | | | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538.
* | Merge pull request #2518 from zachjs/recursionwhitequark2021-01-012-0/+71
|\ \ | | | | | | verilog: improved support for recursive functions
| * | verilog: improved support for recursive functionsZachary Snow2020-12-312-0/+71
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* | | sv: complete support for implied task/function port directionsZachary Snow2020-12-312-0/+29
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* | Fix elaboration of whole memory words used as indicesZachary Snow2020-12-263-0/+48
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* | Fix constants bound to redeclared function argsZachary Snow2020-12-261-0/+10
| | | | | | | | | | | | | | | | The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
* | Merge pull request #2501 from zachjs/genrtlil-tern-signwhitequark2020-12-231-4/+9
|\ \ | | | | | | genrtlil: fix mux2rtlil generated wire signedness
| * | genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-4/+9
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* | | Merge pull request #2476 from zachjs/const-arg-widthwhitequark2020-12-231-0/+10
|\ \ \ | |/ / |/| | Fix constants bound to single bit arguments (fixes #2383)
| * | Fix constants bound to single bit arguments (fixes #2383)Zachary Snow2020-12-221-0/+10
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* | | Merge pull request #2479 from zachjs/const-arg-hintwhitequark2020-12-221-0/+9
|\ \ \ | | | | | | | | Allow constant function calls in constant function arguments
| * | | Allow constant function calls in constant function argumentsZachary Snow2020-12-071-0/+9
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* / / Sign extend port connections where necessaryZachary Snow2020-12-182-0/+98
|/ / | | | | | | | | | | | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* | Merge pull request #2133 from dh73/nodev_headClaire Xen2020-11-2518-65/+322
|\ \ | | | | | | Adding latch tests for shift&mask AST dynamic part-select enhancements
| * | Removing trailing whitespacediego2020-06-101-30/+30
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| * | Adding latch tests for shift&mask AST dynamic part-select enhancementsdiego2020-06-0918-68/+325
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* | | nexus: DSP inference supportDavid Shah2020-11-201-12/+34
| |/ |/| | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Update nexus arch tests to new harnessXiretza2020-10-291-19/+3
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* | xilinx: Fix attributes_test.ysMarcelina Kościelnicka2020-10-241-4/+2
| | | | | | | | | | | | | | | | | | | | This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory.
* | memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+24
| | | | | | | | | | | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* | Merge pull request #2397 from daveshah1/nexusMiodrag Milanović2020-10-1915-0/+298
|\ \ | | | | | | synth_nexus: Initial implementation
| * | synth_nexus: Initial implementationDavid Shah2020-10-1515-0/+298
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | opt_clean: Better memory handling.Marcelina Kościelnicka2020-10-081-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved.
* | | Merge pull request #2378 from udif/pr_dollar_high_lowclairexen2020-10-011-0/+61
|\ \ \ | | | | | | | | Added $high(), $low(), $left(), $right()
| * | | We can now handle array slices (e.g. $size(x[1]) etc. )Udi Finkelstein2020-09-171-2/+14
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| * | | Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-151-0/+49
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* | | | Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-0121-230/+156
|\ \ \ \ | | | | | | | | | | Clean up and parallelize testsuite
| * | | | tests: add gitignores for auto-generated makefilesXiretza2020-09-262-0/+2
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| * | | | tests/simple: remove "nullglob" shoptXiretza2020-09-211-1/+0
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| * | | | tests: ParallelizeXiretza2020-09-213-9/+20
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| * | | | tests: Centralize test collection and Makefile generationXiretza2020-09-2116-222/+136
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* | | | | Update .gitignoreDavid Shah2020-10-011-0/+2
| |_|/ / |/| | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | add testsN. Engelhardt2020-09-282-0/+49
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* | | | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-231-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-10 10:51:24 +0000