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* verilog: improve specify support when not in -specify modeEddie Hung2020-02-132-3/+1
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* verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-0/+6
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* specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-0/+7
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* verilog: fix $specify3 checkEddie Hung2020-02-131-0/+7
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* Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-0/+5
|\ | | | | Fix crash on wire declaration with delay
| * add testcase for #1614Stefan Biereigel2020-02-031-0/+5
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* | Merge pull request #1670 from rodrigomelo9/masterEddie Hung2020-02-104-0/+137
|\ \ | | | | | | $readmem[hb] file inclusion is now relative to the Verilog file
| * | Added 'set -e' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-061-0/+20
| | | | | | | | | | | | | | | | | | Also added two checks for situations where the execution must fail. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | Merge branch 'master' into masterRodrigo A. Melo2020-02-034-4/+84
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| * \ \ Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-032-0/+136
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | | Removed 'synth' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-021-8/+8
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | Added content1.dat into tests/memfileRodrigo Alejandro Melo2020-02-022-21/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified run-test.sh to use it. Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | Added tests/memfile to 'make test' with an extra testcaseRodrigo Alejandro Melo2020-02-011-16/+10
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | Added a test for the Memory Content File inclusion using $readmembRodrigo Alejandro Melo2020-02-013-0/+63
| | |_|/ | |/| | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | | | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* | | | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-1/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* | | | shiftx2mux: fix select out of boundsEddie Hung2020-02-052-1/+12
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* | | | Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-051-0/+49
|\ \ \ \ | | | | | | | | | | opt_merge: discard \init of '$' cells with 'Q' port when merging
| * \ \ \ Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-2874-149/+1770
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| * | | | | Add testcaseEddie Hung2019-12-131-0/+49
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* | | | | | Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-053-5/+115
|\ \ \ \ \ \ | | | | | | | | | | | | | | techmap LSB-first for compatible $shift/$shiftx cells
| * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-0517-30/+474
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| * | | | | | | Update tests with reduced areaEddie Hung2020-01-212-6/+6
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| * | | | | | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-211-4/+4
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| * | | | | | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-211-0/+110
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* | | | | | | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+21
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* | | | | | | Merge pull request #1638 from YosysHQ/eddie/fix1631Eddie Hung2020-02-051-0/+66
|\ \ \ \ \ \ \ | |_|_|_|_|_|/ |/| | | | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
| * | | | | | More rigorous testEddie Hung2020-01-161-7/+34
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| * | | | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*Eddie Hung2020-01-151-0/+39
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* | | | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-034-4/+84
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* | | | | | sv: More tests for wildcard port connectionsDavid Shah2020-02-021-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | hierarchy: Correct handling of wildcard port connections with default valuesDavid Shah2020-02-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | sv: Add tests for wildcard port connectionsDavid Shah2020-02-021-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | Merge pull request #1647 from YosysHQ/dave/sprintfDavid Shah2020-02-021-0/+12
|\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | ast: Add support for $sformatf system function
| * | | | | ast: Add support for $sformatf system functionDavid Shah2020-01-191-0/+12
| | |/ / / | |/| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #1559 from YosysHQ/efinix_test_fixMiodrag Milanović2020-01-291-1/+1
|\ \ \ \ \ | | | | | | | | | | | | Fix for non-deterministic test
| * | | | | Updated test to use assert-maxMiodrag Milanovic2020-01-281-1/+1
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| * | | | | Fix for non-deterministic testMiodrag Milanovic2019-12-071-1/+1
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* | | | | | Add "help -all" and "help -celltypes" sanity testEddie Hung2020-01-281-0/+2
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* | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-282-0/+102
|\ \ \ \ \ | | | | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx
| * | | | | Import tests from #1628Eddie Hung2020-01-272-0/+102
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* | | | | | Merge pull request #1567 from YosysHQ/eddie/sat_init_warningClaire Wolf2020-01-281-0/+11
|\ \ \ \ \ \ | | | | | | | | | | | | | | sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
| * | | | | | Even more obvious testcaseEddie Hung2019-12-111-6/+5
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| * | | | | | Make testcase clearer with \o having its own initEddie Hung2019-12-111-0/+2
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| * | | | | | Add test: 'Warning: ignoring initial value on non-register: \o'Eddie Hung2019-12-111-0/+10
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* | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+5
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | synth_xilinx: error out if tristate without '-iopad'
| * | | | | Add testEddie Hung2019-12-121-0/+5
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* | | | | Merge pull request #1619 from YosysHQ/eddie/abc9_refactorEddie Hung2020-01-273-0/+60
|\ \ \ \ \ | | | | | | | | | | | | Refactor `abc9` pass
| * | | | | simple_abc9 tests to discard whitebox before write for simEddie Hung2020-01-232-2/+3
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| * | | | | Test for (* keep *)-ed abc9_box_idEddie Hung2020-01-231-0/+16
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