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Author
Age
Files
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Merge branch 'master' into xaig
Eddie Hung
2019-04-08
14
-5
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+737
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Liberty file parser now accepts superfluous ;
Niels Moseley
2019-03-27
1
-1
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+1
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Liberty file parser now accepts superfluous ;
Niels Moseley
2019-03-27
3
-2
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+97
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Fix "verific -extnets" for more complex situations
Clifford Wolf
2019-03-26
1
-0
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+22
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Updated the liberty parser to accept [A:B] ranges (AST has not been updated)....
Niels Moseley
2019-03-24
6
-0
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+541
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Merge https://github.com/YosysHQ/yosys into read_aiger
Eddie Hung
2019-03-19
11
-31
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+175
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fix local name resolution in prefix constructs
Zachary Snow
2019-03-18
1
-0
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+56
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Fix handling of task output ports in clocked always blocks, fixes #857
Clifford Wolf
2019-03-07
1
-0
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+19
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Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Jim Lawson
2019-03-04
1
-0
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+1
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Hotfix for "make test"
Clifford Wolf
2019-02-28
1
-1
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+1
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Add "write_verilog -siminit"
Clifford Wolf
2019-02-28
1
-1
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+1
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Fix FIRRTL to Verilog process instance subfield assignment.
Jim Lawson
2019-02-25
3
-3
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+1
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One more merge conflict
Eddie Hung
2019-02-17
1
-6
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+1
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Merge https://github.com/YosysHQ/yosys into read_aiger
Eddie Hung
2019-02-17
5
-8
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+97
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-02-26
5
-1
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+94
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Merge pull request #812 from ucb-bar/arrayhierarchyfixes
Clifford Wolf
2019-02-24
2
-1
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+68
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Address requested changes - don't require non-$ name.
Jim Lawson
2019-02-22
2
-4
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+7
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Fix normal (non-array) hierarchy -auto-top.
Jim Lawson
2019-02-19
2
-1
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+65
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Merge pull request #824 from litghost/fix_reduce_on_ff
Clifford Wolf
2019-02-24
2
-0
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+24
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Fix WREDUCE on FF not fixing ARST_VALUE parameter.
Keith Rothman
2019-02-22
2
-0
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+24
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Fix handling of defparam for when default_nettype is none
Clifford Wolf
2019-02-24
1
-0
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+2
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Uncomment out more tests
Eddie Hung
2019-02-26
1
-25
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+39
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Enable two inout tests
Eddie Hung
2019-02-26
1
-16
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+14
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Add broken testcases
Eddie Hung
2019-02-25
1
-0
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+46
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Revert "tests/simple to also do LUT synth"
Eddie Hung
2019-02-21
1
-1
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+0
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-02-21
1
-4
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+2
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Revert "Add -B option to autotest.sh to append to backend_opts"
Eddie Hung
2019-02-21
1
-4
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+2
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tests/simple to also do LUT synth
Eddie Hung
2019-02-21
1
-0
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+1
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Working simple_abc9 tests
Eddie Hung
2019-02-21
1
-2
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+2
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Add abc9.v testcase to simple_abc9
Eddie Hung
2019-02-21
1
-4
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+46
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Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
Eddie Hung
2019-02-21
1
-21
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+0
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Remove simple_defparam tests
Eddie Hung
2019-02-20
1
-21
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+0
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simple_abc9 tests to now preserve memories
Eddie Hung
2019-02-20
1
-1
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+1
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Move tests/techmap/abc9 to simple_abc9
Eddie Hung
2019-02-20
4
-23
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+0
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Add tests/simple_abc9
Eddie Hung
2019-02-20
1
-0
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+23
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Add a quick abc9 test
Eddie Hung
2019-02-19
4
-0
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+29
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Merge branch 'master' into xaig
Eddie Hung
2019-02-19
5
-8
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+92
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Merge https://github.com/YosysHQ/yosys into dff_init
Eddie Hung
2019-02-17
5
-8
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+93
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Append (instead of over-writing) EXTRA_FLAGS
Jim Lawson
2019-02-15
1
-1
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+1
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Update cells supported for verilog to FIRRTL conversion.
Jim Lawson
2019-02-15
4
-7
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+92
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Support and differentiate between ASCII and binary AIG testing
Eddie Hung
2019-02-08
2
-2
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+6
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Add binary AIGs converted from AAG
Eddie Hung
2019-02-08
14
-0
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+51
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Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig
Eddie Hung
2019-02-06
3
-2
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+67
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Add tests for simple cases using defparam
Eddie Hung
2019-02-06
1
-0
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+21
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Add -B option to autotest.sh to append to backend_opts
Eddie Hung
2019-02-06
1
-2
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+4
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Extend testcase
Eddie Hung
2019-02-06
1
-2
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+34
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Add testcase
Eddie Hung
2019-02-06
1
-0
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+10
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Revert most of autotest.sh; for non *.v use Yosys to translate
Eddie Hung
2019-02-06
1
-7
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+9
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Rename ASCII tests
Eddie Hung
2019-02-06
15
-0
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+0
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Add tests
Eddie Hung
2019-02-04
16
-8
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+109
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