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* Merge branch 'master' into xaigEddie Hung2019-04-0814-5/+737
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| * Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
| * Liberty file parser now accepts superfluous ;Niels Moseley2019-03-273-2/+97
| * Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-0/+22
| * Updated the liberty parser to accept [A:B] ranges (AST has not been updated)....Niels Moseley2019-03-246-0/+541
| * Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-1911-31/+175
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| | * fix local name resolution in prefix constructsZachary Snow2019-03-181-0/+56
| | * Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-0/+19
| | * Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-0/+1
| | * Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| | * Add "write_verilog -siminit"Clifford Wolf2019-02-281-1/+1
| | * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-253-3/+1
| * | One more merge conflictEddie Hung2019-02-171-6/+1
| * | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-175-8/+97
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* | \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-265-1/+94
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| * | | Merge pull request #812 from ucb-bar/arrayhierarchyfixesClifford Wolf2019-02-242-1/+68
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| | * | | Address requested changes - don't require non-$ name.Jim Lawson2019-02-222-4/+7
| | * | | Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-192-1/+65
| * | | | Merge pull request #824 from litghost/fix_reduce_on_ffClifford Wolf2019-02-242-0/+24
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| | * | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter.Keith Rothman2019-02-222-0/+24
| * | | | | Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+2
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* | | | | Uncomment out more testsEddie Hung2019-02-261-25/+39
* | | | | Enable two inout testsEddie Hung2019-02-261-16/+14
* | | | | Add broken testcasesEddie Hung2019-02-251-0/+46
* | | | | Revert "tests/simple to also do LUT synth"Eddie Hung2019-02-211-1/+0
* | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-211-4/+2
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| * | | | Revert "Add -B option to autotest.sh to append to backend_opts"Eddie Hung2019-02-211-4/+2
* | | | | tests/simple to also do LUT synthEddie Hung2019-02-211-0/+1
* | | | | Working simple_abc9 testsEddie Hung2019-02-211-2/+2
* | | | | Add abc9.v testcase to simple_abc9Eddie Hung2019-02-211-4/+46
* | | | | Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaigEddie Hung2019-02-211-21/+0
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| * | | | Remove simple_defparam testsEddie Hung2019-02-201-21/+0
* | | | | simple_abc9 tests to now preserve memoriesEddie Hung2019-02-201-1/+1
* | | | | Move tests/techmap/abc9 to simple_abc9Eddie Hung2019-02-204-23/+0
* | | | | Add tests/simple_abc9Eddie Hung2019-02-201-0/+23
* | | | | Add a quick abc9 testEddie Hung2019-02-194-0/+29
* | | | | Merge branch 'master' into xaigEddie Hung2019-02-195-8/+92
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| * | | Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-175-8/+93
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| | * | Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
| | * | Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-154-7/+92
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* | | Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-082-2/+6
* | | Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
* | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-063-2/+67
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| * | Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
| * | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
| * | Extend testcaseEddie Hung2019-02-061-2/+34
| * | Add testcaseEddie Hung2019-02-061-0/+10
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* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
* | Rename ASCII testsEddie Hung2019-02-0615-0/+0
* | Add testsEddie Hung2019-02-0416-8/+109
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