| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | | | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff | Eddie Hung | 2019-11-21 | 3 | -4/+9 | |
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| | | * | | | | | | | | | | | | async2sync -> clk2fflogic | Eddie Hung | 2019-11-21 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -3/+0 | |
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| | | * | | | | | | | | | | | | Remove redundant flatten | Eddie Hung | 2019-11-22 | 1 | -2/+0 | |
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| | | * | | | | | | | | | | | | Stray dump | Eddie Hung | 2019-11-22 | 1 | -1/+0 | |
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| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+28 | |
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| | | * | | | | | | | | | | | | Add another test with constant driver | Eddie Hung | 2019-11-22 | 1 | -0/+28 | |
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| | * | | | | | | | | | | | | | Add testcase for signal used as part input part output | Eddie Hung | 2019-11-22 | 1 | -0/+5 | |
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| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+25 | |
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| | | * | | | | | | | | | | | | Cleanup spacing | Eddie Hung | 2019-11-22 | 1 | -2/+1 | |
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| | | * | | | | | | | | | | | | Add testcase | Eddie Hung | 2019-11-22 | 1 | -0/+26 | |
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| | * | | | | | | | | | | | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -1/+63 | |
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| | * | | | | | | | | | | | | | Missing endmodule | Eddie Hung | 2019-11-22 | 1 | -0/+1 | |
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| | * | | | | | | | | | | | | | Merge branch 'eddie/xaig_dff_adff' into xaig_dff | Eddie Hung | 2019-11-21 | 3 | -3/+37 | |
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| | | * | | | | | | | | | | | | Add a equiv test too | Eddie Hung | 2019-11-19 | 2 | -0/+23 | |
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| | | * | | | | | | | | | | | | Add two tests | Eddie Hung | 2019-11-19 | 1 | -0/+12 | |
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| | * | | | | | | | | | | | | | Add test | Eddie Hung | 2019-11-21 | 1 | -1/+6 | |
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| | * | | | | | | | | | | | | Add multi clock test | Eddie Hung | 2019-11-20 | 1 | -0/+5 | |
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| * | | | | | | | | | | / | Add testcase from #1459 | Eddie Hung | 2020-01-06 | 1 | -0/+25 | |
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| * | | | | | | | | | | | Merge pull request #1606 from YosysHQ/eddie/improve_tests | Eddie Hung | 2020-01-01 | 9 | -11/+12 | |
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Fix a few issues in tests/arch/* | |||||
| | * | | | | | | | | | | | Revert insertion of 'reg', leave note behind | Eddie Hung | 2020-01-01 | 1 | -1/+2 | |
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| | * | | | | | | | | | | | Do not do call equiv_opt when no sim model exists | Eddie Hung | 2019-12-31 | 2 | -4/+4 | |
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| | * | | | | | | | | | | | Fix warnings | Eddie Hung | 2019-12-31 | 2 | -2/+2 | |
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| | * | | | | | | | | | | | Call equiv_opt with -multiclock and -assert | Eddie Hung | 2019-12-31 | 5 | -5/+5 | |
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| * / | | | | | | | | | | Added a test case | Miodrag Milanovic | 2020-01-01 | 1 | -0/+19 | |
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| * | | | | | | | | | | Merge pull request #1589 from YosysHQ/iopad_default | Miodrag Milanović | 2019-12-30 | 19 | -60/+61 | |
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Make iopad option default for all xilinx flows | |||||
| | * | | | | | | | | | | Fix new tests | Miodrag Milanovic | 2019-12-28 | 3 | -6/+6 | |
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| | * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into iopad_default | Miodrag Milanovic | 2019-12-28 | 5 | -0/+141 | |
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| | * | | | | | | | | | | | Make test without iopads | Miodrag Milanovic | 2019-12-28 | 17 | -51/+51 | |
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| | * | | | | | | | | | | | Revert "Fix xilinx tests, when iopads are default" | Miodrag Milanovic | 2019-12-28 | 16 | -40/+40 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 477e43d921d204c6bc6403109fea6506802c948c. | |||||
| | * | | | | | | | | | | | Addressed review comments | Miodrag Milanovic | 2019-12-21 | 1 | -1/+0 | |
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| | * | | | | | | | | | | | Fix xilinx tests, when iopads are default | Miodrag Milanovic | 2019-12-21 | 17 | -42/+44 | |
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| * | | | | | | | | | | | Merge pull request #1599 from YosysHQ/eddie/retry_1588 | Eddie Hung | 2019-12-30 | 3 | -0/+48 | |
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once" | |||||
| | * | | | | | | | | | | | Add #1598 testcase | Eddie Hung | 2019-12-27 | 3 | -0/+48 | |
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| * / | | | | | | | | | | Update resource count | Eddie Hung | 2019-12-28 | 1 | -3/+3 | |
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| * | | | | | | | | | | iopadmap: Emit tristate buffers with const OE for some edge cases. | Marcin Kościelnicki | 2019-12-25 | 1 | -0/+23 | |
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| * | | | | | | | | | | Add DSP cascade tests | Eddie Hung | 2019-12-23 | 1 | -0/+89 | |
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| * | | | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 3 | -0/+29 | |
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| * | | | | | | | | | Merge pull request #1569 from YosysHQ/eddie/fix_1531 | Eddie Hung | 2019-12-19 | 1 | -0/+34 | |
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | verilog: preserve size of $genval$-s in for loops | |||||
| | * | | | | | | | | | Add testcase | Eddie Hung | 2019-12-11 | 1 | -0/+34 | |
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| * | | | | | | | | | Merge pull request #1571 from YosysHQ/eddie/fix_1570 | Eddie Hung | 2019-12-19 | 1 | -3/+1 | |
| |\ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|/ |/| | | | | | | | | mem_arst.v: do not redeclare ANSI port | |||||
| | * | | | | | | | | Make SV2017 compliant courtesy of @wsnyder | Eddie Hung | 2019-12-12 | 1 | -3/+1 | |
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| * | | | | | | | | Merge pull request #1572 from nakengelhardt/scratchpad_pass | Eddie Hung | 2019-12-18 | 1 | -0/+5 | |
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | add a command to read/modify scratchpad contents | |||||
| | * | | | | | | | | add assert option to scratchpad command | N. Engelhardt | 2019-12-16 | 2 | -14/+5 | |
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| | * | | | | | | | | add test and make help message more verbose | N. Engelhardt | 2019-12-12 | 1 | -0/+14 | |
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| * | | | | | | | | tests/xilinx: fix flaky mux test | Marcin Kościelnicki | 2019-12-18 | 1 | -2/+4 | |
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| * | | | | | | | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 3 | -3/+232 | |
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| * | | | | | | | | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 3 | -11/+12 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | |||||
| * | | | | | | | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram | Eddie Hung | 2019-12-16 | 10 | -53/+228 | |
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M | |||||
| | * | | | | | | | | Disable RAM16X1D test | Eddie Hung | 2019-12-13 | 1 | -17/+17 | |
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index : iCE40/yosys | |
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