From e56dad56c42c9da03d23ba296ed1582dbb4e8b48 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 12 Apr 2023 13:53:42 +0200 Subject: fabulous: Add support for LUT6s Signed-off-by: gatecat --- techlibs/fabulous/cells_map.v | 7 ++++++- techlibs/fabulous/prims.v | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/techlibs/fabulous/cells_map.v b/techlibs/fabulous/cells_map.v index eadd18b6f..e33e641a8 100644 --- a/techlibs/fabulous/cells_map.v +++ b/techlibs/fabulous/cells_map.v @@ -16,10 +16,15 @@ module \$lut (A, Y); end else if (WIDTH == 3) begin LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2])); - end else if (WIDTH == 4) begin LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); + end else + if (WIDTH == 5) begin + LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4])); + end else + if (WIDTH == 6) begin + LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]), .I5(A[5])); end else begin wire _TECHMAP_FAIL_ = 1; end diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v index fe3e8536a..21dc5223d 100644 --- a/techlibs/fabulous/prims.v +++ b/techlibs/fabulous/prims.v @@ -38,6 +38,38 @@ module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci); assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2); endmodule +module LUT5(output O, input I0, I1, I2, I3, I4); + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT6(output O, input I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT55_FCY (output O, Co, input I0, I1, I2, I3, I4, Ci); + parameter [63:0] INIT = 0; + + wire comb1, comb2; + + LUT5 #(.INIT(INIT[31: 0])) l5_1 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb1)); + LUT5 #(.INIT(INIT[63:32])) l5_2 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb2)); + + assign O = comb1 ^ Ci; + assign Co = comb1 ? Ci : comb2; +endmodule + + module LUTFF(input CLK, D, output reg O); initial O = 1'b0; always @ (posedge CLK) begin -- cgit v1.2.3