From fc56978703b5e942ba728970e13e065100a34cd7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Oliver=20Kesz=C3=B6cze?= Date: Fri, 17 Feb 2023 17:54:41 +0100 Subject: Check DREG attribute The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680 --- techlibs/xilinx/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index ee5a89e22..e6e15b16e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -3614,7 +3614,7 @@ module DSP48E1 ( if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end else always @* Cr <= C; - if (CREG == 1) initial Dr = 25'b0; + if (DREG == 1) initial Dr = 25'b0; if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end else always @* Dr <= D; -- cgit v1.2.3