From fbb346ea91a04f2feaf6fa96770fe0cd57020e75 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 4 Jun 2020 10:46:54 +0000 Subject: flatten: preserve original object names via hdlname attribute. --- README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 770c62459..203a292d1 100644 --- a/README.md +++ b/README.md @@ -309,7 +309,9 @@ Verilog Attributes and non-standard features that have ports with a width that depends on a parameter. - The ``hdlname`` attribute is used by some passes to document the original - (HDL) name of a module when renaming a module. + (HDL) name of a module when renaming a module. It should contain a single + name, or, when describing a hierarchical name in a flattened design, multiple + names separated by a single space character. - The ``keep`` attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that -- cgit v1.2.3