From f9946232adf887e5aa4a48c64f88eaa17e424009 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 27 Jul 2014 01:49:51 +0200 Subject: Refactoring: Renamed RTLIL::Module::wires to wires_ --- backends/autotest/autotest.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/autotest') diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc index db49880ae..06b2c2a93 100644 --- a/backends/autotest/autotest.cc +++ b/backends/autotest/autotest.cc @@ -105,7 +105,7 @@ static void autotest(FILE *f, RTLIL::Design *design) int count_ports = 0; log("Generating test bench for module `%s'.\n", it->first.c_str()); - for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) { + for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { RTLIL::Wire *wire = it2->second; if (wire->port_output) { count_ports++; @@ -134,7 +134,7 @@ static void autotest(FILE *f, RTLIL::Design *design) } } fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str()); - for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) { + for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) { RTLIL::Wire *wire = it2->second; if (wire->port_output || wire->port_input) fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(), -- cgit v1.2.3