From fa04b1967076d8a97bdd8802664fd2d1a2424be2 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 11 Jun 2020 12:42:37 +0000 Subject: cxxrtl: expose RTLIL::{Wire,Memory}->start_offset in debug info. --- backends/cxxrtl/cxxrtl_capi.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'backends/cxxrtl/cxxrtl_capi.h') diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h index 8bd906ea4..cdddf63f3 100644 --- a/backends/cxxrtl/cxxrtl_capi.h +++ b/backends/cxxrtl/cxxrtl_capi.h @@ -113,9 +113,15 @@ struct cxxrtl_object { // Width of the object in bits. size_t width; + // Index of the least significant bit. + size_t lsb_at; + // Depth of the object. Only meaningful for memories; for other objects, always 1. size_t depth; + // Index of the first word. Only meaningful for memories; for other objects, always 0; + size_t zero_at; + // Bits stored in the object, as 32-bit chunks, least significant bits first. // // The width is rounded up to a multiple of 32; the padding bits are always set to 0 by -- cgit v1.2.3