From a233762a815fc180b371f699e865a7d7aed77bca Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 19:56:17 +0200 Subject: SigSpec refactoring: renamed chunks and width to __chunks and __width --- backends/ilang/ilang_backend.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backends/ilang/ilang_backend.cc') diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index eaad78695..e1a8bfd49 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -102,11 +102,11 @@ void ILANG_BACKEND::dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool au void ILANG_BACKEND::dump_sigspec(FILE *f, const RTLIL::SigSpec &sig, bool autoint) { - if (sig.chunks.size() == 1) { - dump_sigchunk(f, sig.chunks[0], autoint); + if (sig.__chunks.size() == 1) { + dump_sigchunk(f, sig.__chunks[0], autoint); } else { fprintf(f, "{ "); - for (auto it = sig.chunks.rbegin(); it != sig.chunks.rend(); it++) { + for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) { dump_sigchunk(f, *it, false); fprintf(f, " "); } @@ -314,7 +314,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module if (only_selected) { RTLIL::SigSpec sigs = it->first; sigs.append(it->second); - for (auto &c : sigs.chunks) { + for (auto &c : sigs.__chunks) { if (c.wire == NULL || !design->selected(module, c.wire)) continue; show_conn = true; -- cgit v1.2.3