From 1dcb683fcb7d67b045b7600fdd28ec354b78632b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Nov 2013 21:41:39 +0100 Subject: Write yosys version to output files --- backends/verilog/verilog_backend.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 88a48b584..66a497808 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -803,6 +803,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module) reset_auto_counter(module); active_module = module; + fprintf(f, "\n"); for (auto it = module->processes.begin(); it != module->processes.end(); it++) dump_process(f, indent + " ", it->second, true); @@ -956,6 +957,7 @@ struct VerilogBackend : public Backend { } extra_args(f, filename, args, argidx); + fprintf(f, "/* Generated by %s */\n", yosys_version_str); for (auto it = design->modules.begin(); it != design->modules.end(); it++) { if (it->second->get_bool_attribute("\\placeholder") != placeholders) continue; @@ -964,8 +966,6 @@ struct VerilogBackend : public Backend { log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first)); continue; } - if (it != design->modules.begin()) - fprintf(f, "\n"); log("Dumping module `%s'.\n", it->first.c_str()); dump_module(f, "", it->second); } -- cgit v1.2.3