From 39ee561169ba04374c2c630a5ef5a61537a67c13 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 22 Aug 2013 20:22:19 +0200
Subject: More explicit integer output in verilog backend
---
backends/verilog/verilog_backend.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
(limited to 'backends/verilog/verilog_backend.cc')
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 04a3c7643..da1a7433f 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -155,7 +155,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
width = data.bits.size() - offset;
if (data.str.empty() || width != (int)data.bits.size()) {
if (width == 32 && !no_decimal) {
- uint32_t val = 0;
+ int32_t val = 0;
for (int i = offset+width-1; i >= offset; i--) {
assert(i < (int)data.bits.size());
if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
@@ -163,7 +163,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
if (data.bits[i] == RTLIL::S1)
val |= 1 << (i - offset);
}
- fprintf(f, "%d", (int)val);
+ fprintf(f, "%s32'sd%u", val < 0 ? "-" : "", abs(val));
} else {
dump_bits:
fprintf(f, "%d'b", width);
--
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