From 84bf862f7c58c2b69babf043ff5032f924a3ee4d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 14 Aug 2015 10:56:05 +0200 Subject: Spell check (by Larry Doolittle) --- backends/verilog/verilog_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backends/verilog/verilog_backend.cc') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 9b8064611..e6a86a16a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -284,7 +284,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) f << stringf("[%d:%d] ", wire->width - 1 + wire->start_offset, wire->start_offset); f << stringf("%s;\n", id(wire->name).c_str()); #else - // do not use Verilog-2k "outut reg" syntax in verilog export + // do not use Verilog-2k "output reg" syntax in Verilog export std::string range = ""; if (wire->width != 1) { if (wire->upto) -- cgit v1.2.3