From 6c00704a5ef09be46b1f05e2be477e493f37dd38 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Fri, 14 Aug 2015 13:23:01 -0700 Subject: Another block of spelling fixes Smaller this time --- backends/verilog/verilog_backend.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'backends/verilog') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 28c54ce0b..c04389f63 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -17,7 +17,7 @@ * * --- * - * A simple and straightforward verilog backend. + * A simple and straightforward Verilog backend. * * Note that RTLIL processes can't always be mapped easily to a Verilog * process. Therefore this frontend should only be used to export a @@ -966,7 +966,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) n += wen_width; } } - // Output verilog that looks something like this: + // Output Verilog that looks something like this: // reg [..] _3_; // always @(posedge CLK2) begin // _3_ <= memory[D1ADDR]; -- cgit v1.2.3