From 4f426c2ac48bbb5ae9e92ca046aa20af35d75a52 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 22 Sep 2019 16:52:06 +0000 Subject: write_verilog: do not print (*init*) attributes on regs. If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before. --- backends/verilog/verilog_backend.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'backends') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 7b1db4776..24e397bda 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -371,13 +371,14 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) } } -void dump_attributes(std::ostream &f, std::string indent, dict &attributes, char term = '\n', bool modattr = false, bool as_comment = false) +void dump_attributes(std::ostream &f, std::string indent, dict &attributes, char term = '\n', bool modattr = false, bool regattr = false, bool as_comment = false) { if (noattr) return; if (attr2comment) as_comment = true; for (auto it = attributes.begin(); it != attributes.end(); ++it) { + if (it->first == "\\init" && regattr) continue; f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); f << stringf(" = "); if (modattr && (it->second == State::S0 || it->second == Const(0))) @@ -392,7 +393,7 @@ void dump_attributes(std::ostream &f, std::string indent, dictattributes); + dump_attributes(f, indent, wire->attributes, '\n', /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name)); #if 0 if (wire->port_input && !wire->port_output) f << stringf("%s" "input %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); @@ -1521,7 +1522,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw bool got_default = false; for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { - dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true); + dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true); if ((*it)->compare.size() == 0) { if (got_default) continue; @@ -1686,7 +1687,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } } - dump_attributes(f, indent, module->attributes, '\n', /*attr2comment=*/true); + dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; for (int port_id = 1; keep_running; port_id++) { -- cgit v1.2.3 From f02623abb5d8338f034d7069844418af8912ab0f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Oct 2019 00:04:34 +0200 Subject: Bugfix in smtio vcd handling of $-identifiers Signed-off-by: Clifford Wolf --- backends/smt2/smtio.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'backends') diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index bac68ac70..1df996aa7 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -1032,12 +1032,17 @@ class MkVcd: print("$var integer 32 t smt_step $end", file=self.f) print("$var event 1 ! smt_clock $end", file=self.f) + def vcdescape(n): + if n.startswith("$") or ":" in n: + return "\\" + n + return n + scope = [] for path in sorted(self.nets): key, width = self.nets[path] uipath = list(path) - if "." in uipath[-1]: + if "." in uipath[-1] and not uipath[-1].startswith("$"): uipath = uipath[0:-1] + uipath[-1].split(".") for i in range(len(uipath)): uipath[i] = re.sub(r"\[([^\]]*)\]", r"<\1>", uipath[i]) @@ -1048,15 +1053,13 @@ class MkVcd: while uipath[:-1] != scope: scopename = uipath[len(scope)] - if scopename.startswith("$"): - scopename = "\\" + scopename - print("$scope module %s $end" % scopename, file=self.f) + print("$scope module %s $end" % vcdescape(scopename), file=self.f) scope.append(uipath[len(scope)]) if path in self.clocks and self.clocks[path][1] == "event": - print("$var event 1 %s %s $end" % (key, uipath[-1]), file=self.f) + print("$var event 1 %s %s $end" % (key, vcdescape(uipath[-1])), file=self.f) else: - print("$var wire %d %s %s $end" % (width, key, uipath[-1]), file=self.f) + print("$var wire %d %s %s $end" % (width, key, vcdescape(uipath[-1])), file=self.f) for i in range(len(scope)): print("$upscope $end", file=self.f) -- cgit v1.2.3 From 5110a34dd74bc96c47d4aef47bc155110de2d87e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 4 Nov 2019 14:25:13 +0100 Subject: Fix write_aiger bug added in 524af21 Signed-off-by: Clifford Wolf --- backends/aiger/aiger.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'backends') diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 3e8b14dee..44718baae 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -91,6 +91,9 @@ struct AigerWriter } else if (alias_map.count(bit)) { a = bit2aig(alias_map.at(bit)); + } else + if (initstate_bits.count(bit)) { + a = initstate_ff; } if (bit == State::Sx || bit == State::Sz) -- cgit v1.2.3 From d88cc139a029764cf62d95b2eaaff99e270a134a Mon Sep 17 00:00:00 2001 From: Makai Mann Date: Mon, 11 Nov 2019 16:40:51 -0800 Subject: Add an info string symbol for bad states in btor backend --- backends/btor/btor.cc | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'backends') diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 9e316a055..2babd454c 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1070,7 +1070,16 @@ struct BtorWorker bad_properties.push_back(nid_en_and_not_a); } else { int nid = next_nid++; - btorf("%d bad %d\n", nid, nid_en_and_not_a); + + string infostr = + cell->attributes.count("\\src") + ? cell->attributes.at("\\src") + .decode_string() + .c_str() + : log_id(cell); + + std::replace(infostr.begin(), infostr.end(), ' ', '_'); + btorf("%d bad %d %s\n", nid, nid_en_and_not_a, infostr.c_str()); } btorf_pop(log_id(cell)); -- cgit v1.2.3 From cd44826d5026316d9b44ae33c1fcf0d8faf550c4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Nov 2019 11:57:38 +0100 Subject: Use cell name for btor bad state props when it is a public name Signed-off-by: Clifford Wolf --- backends/btor/btor.cc | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) (limited to 'backends') diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 2babd454c..c1da4b127 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1070,15 +1070,11 @@ struct BtorWorker bad_properties.push_back(nid_en_and_not_a); } else { int nid = next_nid++; - - string infostr = - cell->attributes.count("\\src") - ? cell->attributes.at("\\src") - .decode_string() - .c_str() - : log_id(cell); - - std::replace(infostr.begin(), infostr.end(), ' ', '_'); + string infostr = log_id(cell); + if (infostr[0] == '$' && cell->attributes.count("\\src")) { + infostr = cell->attributes.at("\\src").decode_string().c_str(); + std::replace(infostr.begin(), infostr.end(), ' ', '_'); + } btorf("%d bad %d %s\n", nid, nid_en_and_not_a, infostr.c_str()); } -- cgit v1.2.3 From 3c643c57dfee9956697e8629a746bc04439be5a2 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 15 Nov 2019 03:11:46 +0000 Subject: write_verilog: add -extmem option, to write split memory init files. Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used. --- backends/verilog/verilog_backend.cc | 90 ++++++++++++++++++++++++++++++++----- 1 file changed, 80 insertions(+), 10 deletions(-) (limited to 'backends') diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 24e397bda..54d0f6148 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -33,11 +33,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit; -int auto_name_counter, auto_name_offset, auto_name_digits; +bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit; +int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter; std::map auto_name_map; std::set reg_wires, reg_ct; -std::string auto_prefix; +std::string auto_prefix, extmem_prefix; RTLIL::Module *active_module; dict active_initdata; @@ -1069,14 +1069,64 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset); if (use_init) { - f << stringf("%s" "initial begin\n", indent.c_str()); - for (int i=0; iparameters["\\INIT"].extract(i*width, width); + for (int j=0; j expressions within that clock domain @@ -1777,8 +1827,16 @@ struct VerilogBackend : public Backend { log(" deactivates this feature and instead will write string constants\n"); log(" as binary numbers.\n"); log("\n"); + log(" -extmem\n"); + log(" instead of initializing memories using assignments to individual\n"); + log(" elements, use the '$readmemh' function to read initialization data\n"); + log(" from a file. This data is written to a file named by appending\n"); + log(" a sequential index to the Verilog filename and replacing the extension\n"); + log(" with '.mem', e.g. 'write_verilog -extmem foo.v' writes 'foo-1.mem',\n"); + log(" 'foo-2.mem' and so on.\n"); + log("\n"); log(" -defparam\n"); - log(" Use 'defparam' statements instead of the Verilog-2001 syntax for\n"); + log(" use 'defparam' statements instead of the Verilog-2001 syntax for\n"); log(" cell parameters.\n"); log("\n"); log(" -blackboxes\n"); @@ -1812,6 +1870,7 @@ struct VerilogBackend : public Backend { nodec = false; nohex = false; nostr = false; + extmem = false; defparam = false; decimal = false; siminit = false; @@ -1885,6 +1944,11 @@ struct VerilogBackend : public Backend { nostr = true; continue; } + if (arg == "-extmem") { + extmem = true; + extmem_counter = 1; + continue; + } if (arg == "-defparam") { defparam = true; continue; @@ -1912,6 +1976,12 @@ struct VerilogBackend : public Backend { break; } extra_args(f, filename, args, argidx); + if (extmem) + { + if (filename.empty()) + log_cmd_error("Option -extmem must be used with a filename.\n"); + extmem_prefix = filename.substr(0, filename.rfind('.')); + } design->sort(); -- cgit v1.2.3