From 06df86aae3618cd957a0538693bfabb01487b23d Mon Sep 17 00:00:00 2001 From: Johann Klammer Date: Thu, 23 Feb 2017 19:42:37 +0100 Subject: add options for edif flavors *to force renames on wide ports *to choose array delimiters *to choose up or downwards indices --- backends/edif/edif.cc | 64 +++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 4 deletions(-) (limited to 'backends') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 6414bc6e5..7e6cfd5b7 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -31,8 +31,12 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str() +#define EDIF_DEFR(_id, _ren, _del, _bd) edif_names(RTLIL::unescape_id(_id), true, _ren, _del, _bd).c_str() #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str() +static char const edf_defdel[2] = {'[',']'}; +static int const edf_defbd[2] = {0,1}; + namespace { struct EdifNames @@ -43,10 +47,12 @@ namespace EdifNames() : counter(1) { } - std::string operator()(std::string id, bool define) + std::string operator()(std::string id, bool define, bool always_rename = false, char const delim[2] = edf_defdel, int const bounds[2] = edf_defbd) { if (define) { std::string new_id = operator()(id, false); + if (always_rename) + return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim[0], bounds[0], bounds[1], delim[1]); return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id; } @@ -105,6 +111,25 @@ struct EdifBackend : public Backend { log(" if the design contains constant nets. use \"hilomap\" to map to custom\n"); log(" constant drivers first)\n"); log("\n"); + log(" -pidx {up|down}\n"); + log(" adds rename clauses to all module ports to line up signal and member indices.\n"); + log(" if it is up, a 24 bit port will be renamed as follows:\n"); + log(" (rename mcu_addr \"mcu_addr[0:23]\")\n"); + log(" if it is down, it will be:\n"); + log(" (rename mcu_addr \"mcu_addr[23:0]\")\n"); + log("\n"); + log(" -parray {par|bra|ang}\n"); + log(" sets the delimiting character for module port rename clauses.\n"); + log(" if it is par, The example from above will be:\n"); + log(" (rename mcu_addr \"mcu_addr(0:23)\")\n"); + log(" if it is ang, The example from above will be:\n"); + log(" (rename mcu_addr \"mcu_addr<0:23>\")\n"); + log(" otherwise:\n"); + log(" (rename mcu_addr \"mcu_addr[0:23]\")\n"); + log("\n"); + log(" If neither -parray nor -pidx are given, there will be no port rename clauses."); + log(" If only one is given, -parray will default to bra and -pidx to up."); + log("\n"); log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n"); log("command generates EDIF files for the Xilinx place&route tools. It might be\n"); log("necessary to make small modifications to this command when a different tool\n"); @@ -114,8 +139,10 @@ struct EdifBackend : public Backend { virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) { log_header(design, "Executing EDIF backend.\n"); - std::string top_module_name; + bool always_rename = false; + char delim[2] = {'[',']'}; + int bounds[2] = {0,1}; std::map> lib_cell_ports; bool nogndvcc = false; CellTypes ct(design); @@ -132,6 +159,29 @@ struct EdifBackend : public Backend { nogndvcc = true; continue; } + if (args[argidx] == "-pidx" && argidx+1 < args.size()) { + always_rename = true; + if(args[++argidx] == "down") { + bounds[0]=1;bounds[1]=0; + } + else { + bounds[0]=0;bounds[1]=1; + } + continue; + } + if (args[argidx] == "-parray" && argidx+1 < args.size()) { + std::string parray; + always_rename = true; + parray = args[++argidx]; + if (parray == "par") { + delim[0] = '(';delim[1] = ')'; + } else if (parray == "ang") { + delim[0] = '<';delim[1] = '>'; + } else { + delim[0] = '[';delim[1] = ']'; + } + continue; + } break; } extra_args(f, filename, args, argidx); @@ -215,7 +265,11 @@ struct EdifBackend : public Backend { if (port_it.second == 1) *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir); else - *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(port_it.first), port_it.second, dir); + { + int bd[2]={0,port_it.second-1}; + int b[2]={bd[bounds[0]],bd[bounds[1]]}; + *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, always_rename, delim, b), port_it.second, dir); + } } *f << stringf(" )\n"); *f << stringf(" )\n"); @@ -283,7 +337,9 @@ struct EdifBackend : public Backend { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire)); net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name))); } else { - *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); + int bd[2]={0,wire->width-1}; + int b[2]={bd[bounds[0]],bd[bounds[1]]}; + *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, always_rename, delim, b), wire->width, dir); for (int i = 0; i < wire->width; i++) { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); -- cgit v1.2.3 From 6d7a77dbf6fca96efec4e87a5755d7c3a2f6af2a Mon Sep 17 00:00:00 2001 From: Johann Klammer Date: Fri, 24 Feb 2017 13:18:49 +0100 Subject: Did as you requested, /but/... Now the nets are wired in reverse again because the netlister still uses zero-based indices. --- backends/edif/edif.cc | 74 ++++++++++++++++++++------------------------------- 1 file changed, 29 insertions(+), 45 deletions(-) (limited to 'backends') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 7e6cfd5b7..8cdcddff1 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -31,28 +31,27 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str() -#define EDIF_DEFR(_id, _ren, _del, _bd) edif_names(RTLIL::unescape_id(_id), true, _ren, _del, _bd).c_str() +#define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str() #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str() -static char const edf_defdel[2] = {'[',']'}; -static int const edf_defbd[2] = {0,1}; - namespace { struct EdifNames { int counter; + char delim_left; + char delim_right; std::set generated_names, used_names; std::map name_map; - EdifNames() : counter(1) { } + EdifNames() : counter(1), delim_left('['), delim_right(']') { } - std::string operator()(std::string id, bool define, bool always_rename = false, char const delim[2] = edf_defdel, int const bounds[2] = edf_defbd) + std::string operator()(std::string id, bool define, bool port_rename = false, int range_left = 0, int range_right = 0) { if (define) { std::string new_id = operator()(id, false); - if (always_rename) - return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim[0], bounds[0], bounds[1], delim[1]); + if (port_rename) + return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right); return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id; } @@ -111,14 +110,7 @@ struct EdifBackend : public Backend { log(" if the design contains constant nets. use \"hilomap\" to map to custom\n"); log(" constant drivers first)\n"); log("\n"); - log(" -pidx {up|down}\n"); - log(" adds rename clauses to all module ports to line up signal and member indices.\n"); - log(" if it is up, a 24 bit port will be renamed as follows:\n"); - log(" (rename mcu_addr \"mcu_addr[0:23]\")\n"); - log(" if it is down, it will be:\n"); - log(" (rename mcu_addr \"mcu_addr[23:0]\")\n"); - log("\n"); - log(" -parray {par|bra|ang}\n"); + log(" -pvector {par|bra|ang}\n"); log(" sets the delimiting character for module port rename clauses.\n"); log(" if it is par, The example from above will be:\n"); log(" (rename mcu_addr \"mcu_addr(0:23)\")\n"); @@ -127,9 +119,6 @@ struct EdifBackend : public Backend { log(" otherwise:\n"); log(" (rename mcu_addr \"mcu_addr[0:23]\")\n"); log("\n"); - log(" If neither -parray nor -pidx are given, there will be no port rename clauses."); - log(" If only one is given, -parray will default to bra and -pidx to up."); - log("\n"); log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n"); log("command generates EDIF files for the Xilinx place&route tools. It might be\n"); log("necessary to make small modifications to this command when a different tool\n"); @@ -140,9 +129,7 @@ struct EdifBackend : public Backend { { log_header(design, "Executing EDIF backend.\n"); std::string top_module_name; - bool always_rename = false; - char delim[2] = {'[',']'}; - int bounds[2] = {0,1}; + bool port_rename = false; std::map> lib_cell_ports; bool nogndvcc = false; CellTypes ct(design); @@ -159,26 +146,16 @@ struct EdifBackend : public Backend { nogndvcc = true; continue; } - if (args[argidx] == "-pidx" && argidx+1 < args.size()) { - always_rename = true; - if(args[++argidx] == "down") { - bounds[0]=1;bounds[1]=0; - } - else { - bounds[0]=0;bounds[1]=1; - } - continue; - } - if (args[argidx] == "-parray" && argidx+1 < args.size()) { + if (args[argidx] == "-pvector" && argidx+1 < args.size()) { std::string parray; - always_rename = true; + port_rename = true; parray = args[++argidx]; if (parray == "par") { - delim[0] = '(';delim[1] = ')'; + edif_names.delim_left = '(';edif_names.delim_right = ')'; } else if (parray == "ang") { - delim[0] = '<';delim[1] = '>'; + edif_names.delim_left = '<';edif_names.delim_right = '>'; } else { - delim[0] = '[';delim[1] = ']'; + edif_names.delim_left = '[';edif_names.delim_right = ']'; } continue; } @@ -264,11 +241,17 @@ struct EdifBackend : public Backend { } if (port_it.second == 1) *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir); - else - { - int bd[2]={0,port_it.second-1}; - int b[2]={bd[bounds[0]],bd[bounds[1]]}; - *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, always_rename, delim, b), port_it.second, dir); + else { + int b[2] = {0,port_it.second-1}; + auto m = design->module(cell_it.first); + if(m) { + auto w = m->wire(port_it.first); + if(w) { + b[!w->upto] = w->start_offset; + b[!!w->upto] = w->start_offset+GetSize(w)-1; + } + } + *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), port_it.second, dir); } } *f << stringf(" )\n"); @@ -337,9 +320,10 @@ struct EdifBackend : public Backend { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire)); net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name))); } else { - int bd[2]={0,wire->width-1}; - int b[2]={bd[bounds[0]],bd[bounds[1]]}; - *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, always_rename, delim, b), wire->width, dir); + int b[2] = {0,wire->width-1}; + b[!wire->upto] = wire->start_offset; + b[!!wire->upto] = wire->start_offset+GetSize(wire)-1; + *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir); for (int i = 0; i < wire->width; i++) { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); -- cgit v1.2.3 From 8c61ecdd6e8ea5d2977ff32f118e58a9395616b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 25 Feb 2017 16:28:34 +0100 Subject: Clean up edif code, swap bit indexing of "upto" ports --- backends/edif/edif.cc | 52 ++++++++++++++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 17 deletions(-) (limited to 'backends') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 8cdcddff1..7cf38b775 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -39,8 +39,7 @@ namespace struct EdifNames { int counter; - char delim_left; - char delim_right; + char delim_left, delim_right; std::set generated_names, used_names; std::map name_map; @@ -242,13 +241,13 @@ struct EdifBackend : public Backend { if (port_it.second == 1) *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir); else { - int b[2] = {0,port_it.second-1}; + int b[2] = {port_it.second-1, 0}; auto m = design->module(cell_it.first); - if(m) { + if (m) { auto w = m->wire(port_it.first); - if(w) { - b[!w->upto] = w->start_offset; - b[!!w->upto] = w->start_offset+GetSize(w)-1; + if (w) { + b[w->upto ? 0 : 1] = w->start_offset; + b[w->upto ? 1 : 0] = w->start_offset+GetSize(w)-1; } } *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), port_it.second, dir); @@ -320,13 +319,16 @@ struct EdifBackend : public Backend { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire)); net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name))); } else { - int b[2] = {0,wire->width-1}; - b[!wire->upto] = wire->start_offset; - b[!!wire->upto] = wire->start_offset+GetSize(wire)-1; + int b[2]; + b[wire->upto ? 0 : 1] = wire->start_offset; + b[wire->upto ? 1 : 0] = wire->start_offset + GetSize(wire) - 1; *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir); for (int i = 0; i < wire->width; i++) { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); - net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); + if (wire->upto) + net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1)); + else + net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); } } } @@ -368,18 +370,34 @@ struct EdifBackend : public Backend { i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i])); else if (sig.size() == 1) net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); - else - net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); + else { + int member_idx = i; + auto m = design->module(cell->type); + if (m) { + auto w = m->wire(p.first); + if (w && w->upto) + member_idx = GetSize(w)-i-1; + } + net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", + EDIF_REF(p.first), member_idx, EDIF_REF(cell->name))); + } } } for (auto &it : net_join_db) { RTLIL::SigBit sig = it.first; if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) log_abort(); - std::string netname = log_signal(sig); - for (size_t i = 0; i < netname.size(); i++) - if (netname[i] == ' ' || netname[i] == '\\') - netname.erase(netname.begin() + i--); + std::string netname; + if (sig == RTLIL::State::S0) + netname = "GND_NET"; + else if (sig == RTLIL::State::S1) + netname = "VCC_NET"; + else { + netname = log_signal(sig); + for (size_t i = 0; i < netname.size(); i++) + if (netname[i] == ' ' || netname[i] == '\\') + netname.erase(netname.begin() + i--); + } *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) *f << stringf(" %s\n", ref.c_str()); -- cgit v1.2.3 From dfddf391f93a159c3283a2f3bca9da1316533956 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 25 Feb 2017 16:29:27 +0100 Subject: Move EdifNames out of double-private namespace --- backends/edif/edif.cc | 93 +++++++++++++++++++++++++-------------------------- 1 file changed, 45 insertions(+), 48 deletions(-) (limited to 'backends') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 7cf38b775..f493c49e4 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -34,62 +34,59 @@ PRIVATE_NAMESPACE_BEGIN #define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str() #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str() -namespace +struct EdifNames { - struct EdifNames - { - int counter; - char delim_left, delim_right; - std::set generated_names, used_names; - std::map name_map; + int counter; + char delim_left, delim_right; + std::set generated_names, used_names; + std::map name_map; - EdifNames() : counter(1), delim_left('['), delim_right(']') { } + EdifNames() : counter(1), delim_left('['), delim_right(']') { } - std::string operator()(std::string id, bool define, bool port_rename = false, int range_left = 0, int range_right = 0) - { - if (define) { - std::string new_id = operator()(id, false); - if (port_rename) - return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right); - return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id; - } + std::string operator()(std::string id, bool define, bool port_rename = false, int range_left = 0, int range_right = 0) + { + if (define) { + std::string new_id = operator()(id, false); + if (port_rename) + return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right); + return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id; + } - if (name_map.count(id) > 0) - return name_map.at(id); - if (generated_names.count(id) > 0) - goto do_rename; - if (id == "GND" || id == "VCC") - goto do_rename; + if (name_map.count(id) > 0) + return name_map.at(id); + if (generated_names.count(id) > 0) + goto do_rename; + if (id == "GND" || id == "VCC") + goto do_rename; - for (size_t i = 0; i < id.size(); i++) { - if ('A' <= id[i] && id[i] <= 'Z') - continue; - if ('a' <= id[i] && id[i] <= 'z') - continue; - if ('0' <= id[i] && id[i] <= '9' && i > 0) - continue; - if (id[i] == '_' && i > 0 && i != id.size()-1) - continue; - goto do_rename; - } + for (size_t i = 0; i < id.size(); i++) { + if ('A' <= id[i] && id[i] <= 'Z') + continue; + if ('a' <= id[i] && id[i] <= 'z') + continue; + if ('0' <= id[i] && id[i] <= '9' && i > 0) + continue; + if (id[i] == '_' && i > 0 && i != id.size()-1) + continue; + goto do_rename; + } - used_names.insert(id); - return id; + used_names.insert(id); + return id; - do_rename:; - std::string gen_name; - while (1) { - gen_name = stringf("id%05d", counter++); - if (generated_names.count(gen_name) == 0 && - used_names.count(gen_name) == 0) - break; - } - generated_names.insert(gen_name); - name_map[id] = gen_name; - return gen_name; + do_rename:; + std::string gen_name; + while (1) { + gen_name = stringf("id%05d", counter++); + if (generated_names.count(gen_name) == 0 && + used_names.count(gen_name) == 0) + break; } - }; -} + generated_names.insert(gen_name); + name_map[id] = gen_name; + return gen_name; + } +}; struct EdifBackend : public Backend { EdifBackend() : Backend("edif", "write design to EDIF netlist file") { } -- cgit v1.2.3 From c7d128672846bfbbbb2cdf34ddcb65bd7f296a32 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 25 Feb 2017 16:35:53 +0100 Subject: Improve "write_edif" help message --- backends/edif/edif.cc | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'backends') diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index f493c49e4..e0eea85c9 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -107,13 +107,8 @@ struct EdifBackend : public Backend { log(" constant drivers first)\n"); log("\n"); log(" -pvector {par|bra|ang}\n"); - log(" sets the delimiting character for module port rename clauses.\n"); - log(" if it is par, The example from above will be:\n"); - log(" (rename mcu_addr \"mcu_addr(0:23)\")\n"); - log(" if it is ang, The example from above will be:\n"); - log(" (rename mcu_addr \"mcu_addr<0:23>\")\n"); - log(" otherwise:\n"); - log(" (rename mcu_addr \"mcu_addr[0:23]\")\n"); + log(" sets the delimiting character for module port rename clauses to\n"); + log(" parentheses, square brackets, or angle brackets.\n"); log("\n"); log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n"); log("command generates EDIF files for the Xilinx place&route tools. It might be\n"); -- cgit v1.2.3