From a176ac95ded8b5aa9efb98b7a8e6981c90827d0e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Mar 2019 21:35:57 -0800 Subject: Update igloo2 example to Libero v12.0 Signed-off-by: Clifford Wolf --- examples/igloo2/libero.tcl | 9 ++++----- examples/igloo2/runme.sh | 2 +- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'examples') diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 1f3476316..82e614cd4 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -15,6 +15,7 @@ new_project \ import_files -hdl_source {netlist.vm} import_files -sdc {example.sdc} import_files -io_pdc {example.pdc} +build_design_hierarchy set_option -synth 0 organize_tool_files -tool PLACEROUTE \ @@ -44,10 +45,8 @@ puts "**> VERIFYTIMING" run_tool -name {VERIFYTIMING} puts "<** VERIFYTIMING" -save_project - -# puts "**> export_bitstream" -# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} -# puts "<** export_bitstream" +puts "**> export_bitstream" +export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} +puts "<** export_bitstream" exit 0 diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh index 54247759f..95f2282ba 100644 --- a/examples/igloo2/runme.sh +++ b/examples/igloo2/runme.sh @@ -1,4 +1,4 @@ #!/bin/bash set -ex yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v -LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl +LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl -- cgit v1.2.3 From 107d8848041289bdf3ed85f2ca6c7e02fa9ec774 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Mar 2019 23:54:35 -0800 Subject: Improve igloo2 example Signed-off-by: Clifford Wolf --- examples/igloo2/libero.tcl | 9 +++++++-- examples/igloo2/runme.sh | 4 +++- 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'examples') diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 82e614cd4..6f7d4e24b 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -33,20 +33,25 @@ configure_tool -name PLACEROUTE \ -params EFFORT_LEVEL:false \ -params REPAIR_MIN_DELAY:false +puts "" puts "**> COMPILE" run_tool -name {COMPILE} puts "<** COMPILE" +puts "" puts "**> PLACEROUTE" run_tool -name {PLACEROUTE} puts "<** PLACEROUTE" +puts "" puts "**> VERIFYTIMING" run_tool -name {VERIFYTIMING} puts "<** VERIFYTIMING" -puts "**> export_bitstream" +puts "" +puts "**> BITSTREAM" export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} -puts "<** export_bitstream" +puts "<** BITSTREAM" +puts "" exit 0 diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh index 95f2282ba..a08894e0a 100644 --- a/examples/igloo2/runme.sh +++ b/examples/igloo2/runme.sh @@ -1,4 +1,6 @@ #!/bin/bash set -ex yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v -LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl +export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost} +/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl +cp proj/designer/example/export/example.stp . -- cgit v1.2.3 From 32a901ddf21711e2b2fe2a0a8719ff7f69fd9489 Mon Sep 17 00:00:00 2001 From: Kali Prasad Date: Mon, 4 Mar 2019 23:26:56 +0530 Subject: Added examples/anlogic/ --- examples/anlogic/.gitignore | 4 ++++ examples/anlogic/README | 13 +++++++++++++ examples/anlogic/build.sh | 4 ++++ examples/anlogic/build.tcl | 11 +++++++++++ examples/anlogic/demo.adc | 2 ++ examples/anlogic/demo.v | 18 ++++++++++++++++++ examples/anlogic/demo.ys | 3 +++ 7 files changed, 55 insertions(+) create mode 100644 examples/anlogic/.gitignore create mode 100644 examples/anlogic/README create mode 100755 examples/anlogic/build.sh create mode 100644 examples/anlogic/build.tcl create mode 100644 examples/anlogic/demo.adc create mode 100644 examples/anlogic/demo.v create mode 100644 examples/anlogic/demo.ys (limited to 'examples') diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore new file mode 100644 index 000000000..fa9424cd8 --- /dev/null +++ b/examples/anlogic/.gitignore @@ -0,0 +1,4 @@ +demo.bit +demo_phy.area +full.v +*.log \ No newline at end of file diff --git a/examples/anlogic/README b/examples/anlogic/README new file mode 100644 index 000000000..99143cce0 --- /dev/null +++ b/examples/anlogic/README @@ -0,0 +1,13 @@ +LED Blink project for Anlogic Lichee Tang board. + +Follow the install instructions for the Tang Dynasty IDE from given link below. + +https://tang.sipeed.com/en/getting-started/installing-td-ide/linux/ + + +set TD_HOME env variable to the full path to the TD as follow. + +export TD_HOME= + +then run "bash build.sh" in this directory. + diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh new file mode 100755 index 000000000..8b77a32d6 --- /dev/null +++ b/examples/anlogic/build.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -ex +yosys demo.ys +$TD_HOME/bin/td build.tcl \ No newline at end of file diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl new file mode 100644 index 000000000..db8c3b347 --- /dev/null +++ b/examples/anlogic/build.tcl @@ -0,0 +1,11 @@ +import_device eagle_s20.db -package BG256 +read_verilog full.v -top demo +read_adc demo.adc +optimize_rtl +map_macro +map +pack +place +route +report_area -io_info -file demo_phy.area +bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000 diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc new file mode 100644 index 000000000..c8fbaed3e --- /dev/null +++ b/examples/anlogic/demo.adc @@ -0,0 +1,2 @@ +set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ +set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED \ No newline at end of file diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v new file mode 100644 index 000000000..a7edf4e37 --- /dev/null +++ b/examples/anlogic/demo.v @@ -0,0 +1,18 @@ +module demo ( + input wire CLK_IN, + output wire R_LED +); + parameter time1 = 30'd12_000_000; + reg led_state; + reg [29:0] count; + + always @(posedge CLK_IN)begin + if(count == time1)begin + count<= 30'd0; + led_state <= ~led_state; + end + else + count <= count + 1'b1; + end + assign R_LED = led_state; +endmodule \ No newline at end of file diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys new file mode 100644 index 000000000..5687bcd31 --- /dev/null +++ b/examples/anlogic/demo.ys @@ -0,0 +1,3 @@ +read_verilog demo.v +synth_anlogic -top demo +write_verilog full.v \ No newline at end of file -- cgit v1.2.3 From 3ef427f4a96ac8f890cf94079315e172db409526 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Mar 2019 15:21:04 -0800 Subject: Add missing newline Signed-off-by: Clifford Wolf --- examples/anlogic/build.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'examples') diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh index 8b77a32d6..e0f6b4cfe 100755 --- a/examples/anlogic/build.sh +++ b/examples/anlogic/build.sh @@ -1,4 +1,4 @@ #!/bin/bash set -ex yosys demo.ys -$TD_HOME/bin/td build.tcl \ No newline at end of file +$TD_HOME/bin/td build.tcl -- cgit v1.2.3 From 24d1b92eda20269da7ee7ae713f3ab92b8865349 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Mar 2019 17:27:58 -0800 Subject: Improve igloo2 exmaple Signed-off-by: Clifford Wolf --- examples/igloo2/example.pdc | 7 +++++++ examples/igloo2/example.sdc | 1 + examples/igloo2/example.v | 12 ++++++------ examples/igloo2/libero.tcl | 4 ++-- 4 files changed, 16 insertions(+), 8 deletions(-) (limited to 'examples') diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc index e6ffd53db..0cf34adb3 100644 --- a/examples/igloo2/example.pdc +++ b/examples/igloo2/example.pdc @@ -1 +1,8 @@ # Add placement constraints here +set_io clk -pinname H16 -fixed yes -DIRECTION INPUT +set_io SW1 -pinname H12 -fixed yes -DIRECTION INPUT +set_io SW2 -pinname H13 -fixed yes -DIRECTION INPUT +set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT +set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT +set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT +set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc index c6ff94161..f8b487316 100644 --- a/examples/igloo2/example.sdc +++ b/examples/igloo2/example.sdc @@ -1 +1,2 @@ # Add timing constraints here +create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}] diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index 1a1967d5a..b701c707d 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -1,23 +1,23 @@ module example ( input clk, - input EN, + input SW1, + input SW2, output LED1, output LED2, output LED3, - output LED4, - output LED5 + output LED4 ); - localparam BITS = 5; + localparam BITS = 4; localparam LOG2DELAY = 22; reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; always @(posedge clk) begin - counter <= counter + EN; + counter <= counter + SW1 + SW2 + 1; outcnt <= counter >> LOG2DELAY; end - assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1); + assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1); endmodule diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 6f7d4e24b..abc94e479 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -8,8 +8,8 @@ new_project \ -block_mode 0 \ -hdl "VERILOG" \ -family IGLOO2 \ - -die PA4MGL500 \ - -package tq144 \ + -die PA4MGL2500 \ + -package vf256 \ -speed -1 import_files -hdl_source {netlist.vm} -- cgit v1.2.3 From 7c03b0b08209c7e1b3972a05db63b23c0b1d7a5e Mon Sep 17 00:00:00 2001 From: Kali Prasad Date: Wed, 6 Mar 2019 09:51:11 +0530 Subject: examples/anlogic/ now also output the SVF file. --- examples/anlogic/.gitignore | 5 ++++- examples/anlogic/README | 1 - examples/anlogic/build.tcl | 2 +- examples/anlogic/demo.adc | 2 +- examples/anlogic/demo.v | 10 +++++----- examples/anlogic/demo.ys | 2 +- 6 files changed, 12 insertions(+), 10 deletions(-) (limited to 'examples') diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore index fa9424cd8..97c978a15 100644 --- a/examples/anlogic/.gitignore +++ b/examples/anlogic/.gitignore @@ -1,4 +1,7 @@ demo.bit demo_phy.area full.v -*.log \ No newline at end of file +*.log +*.h +*.tde +*.svf diff --git a/examples/anlogic/README b/examples/anlogic/README index 99143cce0..35d8e9cb1 100644 --- a/examples/anlogic/README +++ b/examples/anlogic/README @@ -10,4 +10,3 @@ set TD_HOME env variable to the full path to the TD as fo export TD_HOME= then run "bash build.sh" in this directory. - diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl index db8c3b347..06db525c9 100644 --- a/examples/anlogic/build.tcl +++ b/examples/anlogic/build.tcl @@ -8,4 +8,4 @@ pack place route report_area -io_info -file demo_phy.area -bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000 +bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000 diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc index c8fbaed3e..ec802502e 100644 --- a/examples/anlogic/demo.adc +++ b/examples/anlogic/demo.adc @@ -1,2 +1,2 @@ set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ -set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED \ No newline at end of file +set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v index a7edf4e37..e17db771e 100644 --- a/examples/anlogic/demo.v +++ b/examples/anlogic/demo.v @@ -1,18 +1,18 @@ module demo ( - input wire CLK_IN, - output wire R_LED + input wire CLK_IN, + output wire R_LED ); parameter time1 = 30'd12_000_000; reg led_state; reg [29:0] count; - + always @(posedge CLK_IN)begin if(count == time1)begin - count<= 30'd0; + count<= 30'd0; led_state <= ~led_state; end else count <= count + 1'b1; end assign R_LED = led_state; -endmodule \ No newline at end of file +endmodule diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys index 5687bcd31..cb396cc2b 100644 --- a/examples/anlogic/demo.ys +++ b/examples/anlogic/demo.ys @@ -1,3 +1,3 @@ read_verilog demo.v synth_anlogic -top demo -write_verilog full.v \ No newline at end of file +write_verilog full.v -- cgit v1.2.3 From da5181a3df6ceed96f1762e4cdaec5cbe3ea23db Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Mar 2019 19:49:39 -0800 Subject: Improvements in SF2 flow and demo Signed-off-by: Clifford Wolf --- examples/igloo2/.gitignore | 1 + examples/igloo2/runme.sh | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'examples') diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore index ea58efc9f..33b7182d3 100644 --- a/examples/igloo2/.gitignore +++ b/examples/igloo2/.gitignore @@ -1,3 +1,4 @@ /netlist.edn /netlist.vm +/example.stp /proj diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh index a08894e0a..838f027db 100644 --- a/examples/igloo2/runme.sh +++ b/examples/igloo2/runme.sh @@ -1,6 +1,6 @@ #!/bin/bash set -ex -yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v +yosys -p 'synth_sf2 -noclkbuf -top example -edif netlist.edn -vlog netlist.vm' example.v export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost} /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl cp proj/designer/example/export/example.stp . -- cgit v1.2.3 From e22afeae907e6340aac7797f60c309916fd72097 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Mar 2019 20:35:48 -0800 Subject: Improve igloo2 example Signed-off-by: Clifford Wolf --- examples/igloo2/example.pdc | 12 ++++++++++++ examples/igloo2/example.v | 44 ++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 54 insertions(+), 2 deletions(-) (limited to 'examples') diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc index 0cf34adb3..298d9e934 100644 --- a/examples/igloo2/example.pdc +++ b/examples/igloo2/example.pdc @@ -1,8 +1,20 @@ # Add placement constraints here + set_io clk -pinname H16 -fixed yes -DIRECTION INPUT + set_io SW1 -pinname H12 -fixed yes -DIRECTION INPUT set_io SW2 -pinname H13 -fixed yes -DIRECTION INPUT + set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT + +set_io AA -pinname L12 -fixed yes -DIRECTION OUTPUT +set_io AB -pinname L13 -fixed yes -DIRECTION OUTPUT +set_io AC -pinname M13 -fixed yes -DIRECTION OUTPUT +set_io AD -pinname N15 -fixed yes -DIRECTION OUTPUT +set_io AE -pinname L11 -fixed yes -DIRECTION OUTPUT +set_io AF -pinname L14 -fixed yes -DIRECTION OUTPUT +set_io AG -pinname N14 -fixed yes -DIRECTION OUTPUT +set_io CA -pinname M15 -fixed yes -DIRECTION OUTPUT diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index b701c707d..05b6ced5e 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -5,10 +5,13 @@ module example ( output LED1, output LED2, output LED3, - output LED4 + output LED4, + + output AA, AB, AC, AD, + output AE, AF, AG, CA ); - localparam BITS = 4; + localparam BITS = 8; localparam LOG2DELAY = 22; reg [BITS+LOG2DELAY-1:0] counter = 0; @@ -20,4 +23,41 @@ module example ( end assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1); + + // seg7enc seg7encinst ( + // .seg({AA, AB, AC, AD, AE, AF, AG}), + // .dat(CA ? outcnt[3:0] : outcnt[7:4]) + // ); + + assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[7:4]); + assign CA = counter[10]; +endmodule + +module seg7enc ( + input [3:0] dat, + output [6:0] seg +); + reg [6:0] seg_inv; + always @* begin + seg_inv = 0; + case (dat) + 4'h0: seg_inv = 7'b 0111111; + 4'h1: seg_inv = 7'b 0000110; + 4'h2: seg_inv = 7'b 1011011; + 4'h3: seg_inv = 7'b 1001111; + 4'h4: seg_inv = 7'b 1100110; + 4'h5: seg_inv = 7'b 1101101; + 4'h6: seg_inv = 7'b 1111101; + 4'h7: seg_inv = 7'b 0000111; + 4'h8: seg_inv = 7'b 1111111; + 4'h9: seg_inv = 7'b 1101111; + 4'hA: seg_inv = 7'b 1110111; + 4'hB: seg_inv = 7'b 1111100; + 4'hC: seg_inv = 7'b 0111001; + 4'hD: seg_inv = 7'b 1011110; + 4'hE: seg_inv = 7'b 1111001; + 4'hF: seg_inv = 7'b 1110001; + endcase + end + assign seg = ~seg_inv; endmodule -- cgit v1.2.3 From b1b9edf5cc9e280346ffa0132d570a8ff656eb22 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Mar 2019 20:47:07 -0800 Subject: Improve igloo2 example Signed-off-by: Clifford Wolf --- examples/igloo2/example.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'examples') diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index 05b6ced5e..4a9486e50 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -24,13 +24,14 @@ module example ( assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1); + // assign CA = counter[10]; // seg7enc seg7encinst ( // .seg({AA, AB, AC, AD, AE, AF, AG}), // .dat(CA ? outcnt[3:0] : outcnt[7:4]) // ); - assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[7:4]); - assign CA = counter[10]; + assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]); + assign CA = outcnt[7]; endmodule module seg7enc ( -- cgit v1.2.3 From 78762316aabf6d6fb55cfd4ab5b5a161a69ba203 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 6 Mar 2019 00:41:02 -0800 Subject: Refactor SF2 iobuf insertion, Add clkint insertion Signed-off-by: Clifford Wolf --- examples/igloo2/runme.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'examples') diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh index 838f027db..a08894e0a 100644 --- a/examples/igloo2/runme.sh +++ b/examples/igloo2/runme.sh @@ -1,6 +1,6 @@ #!/bin/bash set -ex -yosys -p 'synth_sf2 -noclkbuf -top example -edif netlist.edn -vlog netlist.vm' example.v +yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost} /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl cp proj/designer/example/export/example.stp . -- cgit v1.2.3