From 53fc3ed64563045949bcd52a03d2af586605d523 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 9 Apr 2020 14:31:14 -0700 Subject: aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created according to mergeability class, and init state as cell attr --- frontends/aiger/aigerparse.cc | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 6fda92d73..7e5e6dd2d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -454,6 +454,14 @@ void AigerReader::parse_xaiger() for (unsigned i = 0; i < flopNum; i++) mergeability.emplace_back(parse_xaiger_literal(f)); } + else if (c == 's') { + uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + flopNum = parse_xaiger_literal(f); + log_assert(dataSize == (flopNum+1) * sizeof(uint32_t)); + initial_state.reserve(flopNum); + for (unsigned i = 0; i < flopNum; i++) + initial_state.emplace_back(parse_xaiger_literal(f)); + } else if (c == 'n') { parse_xaiger_literal(f); f >> s; @@ -767,6 +775,7 @@ void AigerReader::post_process() } } + dict mergeability_to_clock; for (uint32_t i = 0; i < flopNum; i++) { RTLIL::Wire *d = outputs[outputs.size() - flopNum + i]; log_assert(d); @@ -778,10 +787,22 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_)); + Cell* ff; + int clock_index = mergeability[i]; + if (clock_index < 0) { + ff = module->addCell(NEW_ID, ID($_DFF_N_)); + clock_index = -clock_index; + } + else if (clock_index > 0) + ff = module->addCell(NEW_ID, ID($_DFF_P_)); + else log_abort(); + auto r = mergeability_to_clock.insert(clock_index); + if (r.second) + r.first->second = module->addWire(NEW_ID); + ff->setPort(ID::C, r.first->second); ff->setPort(ID::D, d); ff->setPort(ID::Q, q); - ff->attributes[ID::abc9_mergeability] = mergeability[i]; + ff->attributes[ID::abc9_init] = initial_state[i]; } dict> wideports_cache; -- cgit v1.2.3 From 483a190c1b468b2a22fe7f2b92075953c6095f7d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 13 Apr 2020 13:11:25 -0700 Subject: aiger: -xaiger to parse initial state back into (* init *) on Q wire --- frontends/aiger/aigerparse.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7e5e6dd2d..ed3a926c6 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -802,7 +802,8 @@ void AigerReader::post_process() ff->setPort(ID::C, r.first->second); ff->setPort(ID::D, d); ff->setPort(ID::Q, q); - ff->attributes[ID::abc9_init] = initial_state[i]; + log_assert(GetSize(q) == 1); + q->attributes[ID::init] = initial_state[i]; } dict> wideports_cache; -- cgit v1.2.3 From 6f4f795953b2a38ec77984c7e1b50f579b59272e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 15 Apr 2020 12:15:36 -0700 Subject: aiger/xaiger: use odd for negedge clk, even for posedge Since abc9 doesn't like negative mergeability values --- frontends/aiger/aigerparse.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index ed3a926c6..16e94c394 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -789,13 +789,12 @@ void AigerReader::post_process() Cell* ff; int clock_index = mergeability[i]; - if (clock_index < 0) { + if (clock_index & 1) { ff = module->addCell(NEW_ID, ID($_DFF_N_)); - clock_index = -clock_index; + clock_index--; } - else if (clock_index > 0) + else ff = module->addCell(NEW_ID, ID($_DFF_P_)); - else log_abort(); auto r = mergeability_to_clock.insert(clock_index); if (r.second) r.first->second = module->addWire(NEW_ID); -- cgit v1.2.3 From 4017cc6380c3b13f416e55e4e65cf98e7caf45e1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 14:01:54 -0700 Subject: aiger: -xaiger to return $_FF_ flops --- frontends/aiger/aigerparse.cc | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 16e94c394..d25587e48 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -787,21 +787,8 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - Cell* ff; - int clock_index = mergeability[i]; - if (clock_index & 1) { - ff = module->addCell(NEW_ID, ID($_DFF_N_)); - clock_index--; - } - else - ff = module->addCell(NEW_ID, ID($_DFF_P_)); - auto r = mergeability_to_clock.insert(clock_index); - if (r.second) - r.first->second = module->addWire(NEW_ID); - ff->setPort(ID::C, r.first->second); - ff->setPort(ID::D, d); - ff->setPort(ID::Q, q); - log_assert(GetSize(q) == 1); + Cell* ff = module->addFfGate(NEW_ID, d, q); + ff->attributes[ID::abc9_mergeability] = mergeability[i]; q->attributes[ID::init] = initial_state[i]; } -- cgit v1.2.3