From f1a206ba03c5b6fba2672754d09cc649a60beeb8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 20 Aug 2019 18:17:14 -0700 Subject: Revert "Remove sequential extension" This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c. --- frontends/aiger/aigerparse.cc | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index e8ee487e5..7a467b91e 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -732,12 +732,19 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { pool seen_boxes; - unsigned ci_count = 0, co_count = 0; + pool flops; + unsigned ci_count = 0, co_count = 0, flop_count = 0; for (auto cell : boxes) { RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); + bool is_flop = false; if (seen_boxes.insert(cell->type).second) { + if (box_module->attributes.count("\\abc_flop")) { + log_assert(flop_count < flopNum); + flops.insert(cell->type); + is_flop = true; + } auto it = box_module->attributes.find("\\abc_carry"); if (it != box_module->attributes.end()) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; @@ -777,6 +784,8 @@ void AigerReader::post_process() carry_out->port_id = ports.size(); } } + else + is_flop = flops.count(cell->type); // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) @@ -803,7 +812,25 @@ void AigerReader::post_process() rhs.append(wire); } - cell->setPort(port_name, rhs); + if (!is_flop || port_name != "\\$pastQ") + cell->setPort(port_name, rhs); + } + + if (is_flop) { + RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count]; + log_assert(d); + log_assert(d->port_output); + d->port_output = false; + + RTLIL::Wire *q = inputs[piNum - flopNum + flop_count]; + log_assert(q); + log_assert(q->port_input); + q->port_input = false; + + flop_count++; + module->connect(q, d); + cell->set_bool_attribute("\\abc_flop"); + continue; } } @@ -907,6 +934,10 @@ void AigerReader::post_process() } } log_debug(" -> %s\n", log_id(wire)); + int init; + mf >> init; + if (init < 2) + wire->attributes["\\init"] = init; } else if (type == "box") { RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); -- cgit v1.2.3 From 79b6edb6397c530a7304eb4334f95324a4208aba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 28 Sep 2019 23:48:17 -0700 Subject: Big rework; flop info now mostly in cells_sim.v --- frontends/aiger/aigerparse.cc | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7a467b91e..439311230 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -740,7 +740,7 @@ void AigerReader::post_process() bool is_flop = false; if (seen_boxes.insert(cell->type).second) { - if (box_module->attributes.count("\\abc_flop")) { + if (box_module->attributes.count("\\abc9_flop")) { log_assert(flop_count < flopNum); flops.insert(cell->type); is_flop = true; @@ -811,12 +811,18 @@ void AigerReader::post_process() } rhs.append(wire); } - - if (!is_flop || port_name != "\\$pastQ") - cell->setPort(port_name, rhs); + cell->setPort(port_name, rhs); } if (is_flop) { + Wire* port = box_module->wire("\\$currQ"); + log_assert(port); + log_assert(co_count < outputs.size()); + Wire *wire = outputs[co_count++]; + log_assert(wire); + log_assert(wire->port_output); + wire->port_output = false; + RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count]; log_assert(d); log_assert(d->port_output); @@ -827,9 +833,10 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; + auto ff = module->addCell(NEW_ID, "$__ABC_FF_"); + ff->setPort("\\D", d); + ff->setPort("\\Q", q); flop_count++; - module->connect(q, d); - cell->set_bool_attribute("\\abc_flop"); continue; } } -- cgit v1.2.3 From f9bb3352944275acc6e82eaf53aebf3c964f68c4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 16:36:42 -0700 Subject: Cleanup $currQ from aigerparse --- frontends/aiger/aigerparse.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d40f33447..594bf60ce 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -817,8 +817,6 @@ void AigerReader::post_process() } if (is_flop) { - Wire* port = box_module->wire("\\$currQ"); - log_assert(port); log_assert(co_count < outputs.size()); Wire *wire = outputs[co_count++]; log_assert(wire); -- cgit v1.2.3 From 7959e9d6b25d7afefded4b14e14ccf2b0b5af553 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 4 Oct 2019 17:21:14 -0700 Subject: Fix merge issues --- frontends/aiger/aigerparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 77a49c34f..4b66af3ad 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -833,7 +833,7 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - auto ff = module->addCell(NEW_ID, "$__ABC_FF_"); + auto ff = module->addCell(NEW_ID, "$__ABC9_FF_"); ff->setPort("\\D", d); ff->setPort("\\Q", q); flop_count++; -- cgit v1.2.3 From a5767474830756319ce0fff53b81573701ec0cd2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Nov 2019 15:40:46 -0800 Subject: Consistent log message, ignore 's' extension --- frontends/aiger/aigerparse.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 4b66af3ad..9374f1ab3 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -432,7 +432,7 @@ void AigerReader::parse_xaiger(const dict &box_lookup) else if (c == 'r') { uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); flopNum = parse_xaiger_literal(f); - log_debug("flopNum: %u\n", flopNum); + log_debug("flopNum = %u\n", flopNum); log_assert(dataSize == (flopNum+1) * sizeof(uint32_t)); f.ignore(flopNum * sizeof(uint32_t)); } @@ -464,9 +464,10 @@ void AigerReader::parse_xaiger(const dict &box_lookup) boxes.emplace_back(cell); } } - else if (c == 'a' || c == 'i' || c == 'o') { + else if (c == 'a' || c == 'i' || c == 'o' || c == 's') { uint32_t dataSize = parse_xaiger_literal(f); f.ignore(dataSize); + log_debug("ignoring '%c'\n", c); } else { break; -- cgit v1.2.3 From 69d8c1386a239372a2ab8910bf12d5d70701b7fa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Dec 2019 16:21:06 -0800 Subject: Do not connect undriven POs to 1'bx --- frontends/aiger/aigerparse.cc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 9374f1ab3..084107b35 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -1005,15 +1005,10 @@ void AigerReader::post_process() if (other_wire) { other_wire->port_input = false; other_wire->port_output = false; - } - if (wire->port_input) { - if (other_wire) + if (wire->port_input) module->connect(other_wire, SigSpec(wire, i)); - } - else { - // Since we skip POs that are connected to Sx, - // re-connect them here - module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx)); + else + module->connect(SigSpec(wire, i), other_wire); } } } -- cgit v1.2.3 From ab667d3d47ceb07a41b571517b4effb0f4a4bf0b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Dec 2019 16:35:57 -0800 Subject: Call abc9 with "&write -n", and parse_xaiger() to cope --- frontends/aiger/aigerparse.cc | 177 ++++++++++++++++++++---------------------- 1 file changed, 85 insertions(+), 92 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 084107b35..8ff690464 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -376,105 +376,98 @@ void AigerReader::parse_xaiger(const dict &box_lookup) if (n0) module->connect(n0, State::S0); + int c = f.get(); + if (c != 'c') + log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); + c = f.get(); + log_assert(c == '\n'); + // Parse footer (symbol table, comments, etc.) std::string s; - bool comment_seen = false; - for (int c = f.peek(); c != EOF; c = f.peek()) { - if (comment_seen || c == 'c') { - if (!comment_seen) { - f.ignore(1); - c = f.peek(); - comment_seen = true; - } - if (c == '\n') - break; - f.ignore(1); - // XAIGER extensions - if (c == 'm') { - uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); - uint32_t lutNum = parse_xaiger_literal(f); - uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); - log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize); - ConstEvalAig ce(module); - for (unsigned i = 0; i < lutNum; ++i) { - uint32_t rootNodeID = parse_xaiger_literal(f); - uint32_t cutLeavesM = parse_xaiger_literal(f); - log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM); - RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID)); - uint32_t nodeID; - RTLIL::SigSpec input_sig; - for (unsigned j = 0; j < cutLeavesM; ++j) { - nodeID = parse_xaiger_literal(f); - log_debug2("\t%u\n", nodeID); - RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID)); - log_assert(wire); - input_sig.append(wire); - } - // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size()) - ce.clear(); - ce.compute_deps(output_sig, input_sig.to_sigbit_pool()); - RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size()); - for (int j = 0; j < (1 << cutLeavesM); ++j) { - int gray = j ^ (j >> 1); - ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast(cutLeavesM)}); - RTLIL::SigBit o(output_sig); - bool success YS_ATTRIBUTE(unused) = ce.eval(o); - log_assert(success); - log_assert(o.wire == nullptr); - lut_mask[gray] = o.data; - } - RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID)); - log_assert(output_cell); - module->remove(output_cell); - module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask)); + for (int c = f.get(); c != EOF; c = f.get()) { + // XAIGER extensions + if (c == 'm') { + uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + uint32_t lutNum = parse_xaiger_literal(f); + uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize); + ConstEvalAig ce(module); + for (unsigned i = 0; i < lutNum; ++i) { + uint32_t rootNodeID = parse_xaiger_literal(f); + uint32_t cutLeavesM = parse_xaiger_literal(f); + log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM); + RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID)); + uint32_t nodeID; + RTLIL::SigSpec input_sig; + for (unsigned j = 0; j < cutLeavesM; ++j) { + nodeID = parse_xaiger_literal(f); + log_debug2("\t%u\n", nodeID); + RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID)); + log_assert(wire); + input_sig.append(wire); } - } - else if (c == 'r') { - uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); - flopNum = parse_xaiger_literal(f); - log_debug("flopNum = %u\n", flopNum); - log_assert(dataSize == (flopNum+1) * sizeof(uint32_t)); - f.ignore(flopNum * sizeof(uint32_t)); - } - else if (c == 'n') { - parse_xaiger_literal(f); - f >> s; - log_debug("n: '%s'\n", s.c_str()); - } - else if (c == 'h') { - f.ignore(sizeof(uint32_t)); - uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); - log_assert(version == 1); - uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); - log_debug("ciNum = %u\n", ciNum); - uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); - log_debug("coNum = %u\n", coNum); - piNum = parse_xaiger_literal(f); - log_debug("piNum = %u\n", piNum); - uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); - log_debug("poNum = %u\n", poNum); - uint32_t boxNum = parse_xaiger_literal(f); - log_debug("boxNum = %u\n", boxNum); - for (unsigned i = 0; i < boxNum; i++) { - f.ignore(2*sizeof(uint32_t)); - uint32_t boxUniqueId = parse_xaiger_literal(f); - log_assert(boxUniqueId > 0); - uint32_t oldBoxNum = parse_xaiger_literal(f); - RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId)); - boxes.emplace_back(cell); + // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size()) + ce.clear(); + ce.compute_deps(output_sig, input_sig.to_sigbit_pool()); + RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size()); + for (int j = 0; j < (1 << cutLeavesM); ++j) { + int gray = j ^ (j >> 1); + ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast(cutLeavesM)}); + RTLIL::SigBit o(output_sig); + bool success YS_ATTRIBUTE(unused) = ce.eval(o); + log_assert(success); + log_assert(o.wire == nullptr); + lut_mask[gray] = o.data; } + RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID)); + log_assert(output_cell); + module->remove(output_cell); + module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask)); } - else if (c == 'a' || c == 'i' || c == 'o' || c == 's') { - uint32_t dataSize = parse_xaiger_literal(f); - f.ignore(dataSize); - log_debug("ignoring '%c'\n", c); - } - else { - break; + } + else if (c == 'r') { + uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + flopNum = parse_xaiger_literal(f); + log_debug("flopNum = %u\n", flopNum); + log_assert(dataSize == (flopNum+1) * sizeof(uint32_t)); + f.ignore(flopNum * sizeof(uint32_t)); + } + else if (c == 'n') { + parse_xaiger_literal(f); + f >> s; + log_debug("n: '%s'\n", s.c_str()); + } + else if (c == 'h') { + f.ignore(sizeof(uint32_t)); + uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + log_assert(version == 1); + uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + log_debug("ciNum = %u\n", ciNum); + uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + log_debug("coNum = %u\n", coNum); + piNum = parse_xaiger_literal(f); + log_debug("piNum = %u\n", piNum); + uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f); + log_debug("poNum = %u\n", poNum); + uint32_t boxNum = parse_xaiger_literal(f); + log_debug("boxNum = %u\n", boxNum); + for (unsigned i = 0; i < boxNum; i++) { + f.ignore(2*sizeof(uint32_t)); + uint32_t boxUniqueId = parse_xaiger_literal(f); + log_assert(boxUniqueId > 0); + uint32_t oldBoxNum = parse_xaiger_literal(f); + RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId)); + boxes.emplace_back(cell); } } - else - log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); + else if (c == 'a' || c == 'i' || c == 'o' || c == 's') { + uint32_t dataSize = parse_xaiger_literal(f); + f.ignore(dataSize); + log_debug("ignoring '%c'\n", c); + } + else { + break; + } } post_process(); -- cgit v1.2.3 From c0339bbbf16cee8121417f69305c7601122ff70c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 16:21:09 -0800 Subject: Name inputs/outputs of aiger 'i%d' and 'o%d' --- frontends/aiger/aigerparse.cc | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 8ff690464..65a9e30ae 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -610,11 +610,12 @@ void AigerReader::parse_aiger_binary() std::string line; // Parse inputs + int digits = ceil(log10(I)); for (unsigned i = 1; i <= I; ++i) { log_debug2("%d is an input\n", i); - RTLIL::Wire *wire = createWireIfNotExists(module, i << 1); + RTLIL::Wire *wire = module->addWire(stringf("\\i%0*d", digits, i)); wire->port_input = true; - log_assert(!wire->port_output); + module->connect(createWireIfNotExists(module, i << 1), wire); inputs.push_back(wire); } @@ -664,23 +665,15 @@ void AigerReader::parse_aiger_binary() } // Parse outputs + digits = ceil(log10(O)); for (unsigned i = 0; i < O; ++i, ++line_count) { if (!(f >> l1)) log_error("Line %u cannot be interpreted as an output!\n", line_count); log_debug2("%d is an output\n", l1); - const unsigned variable = l1 >> 1; - const bool invert = l1 & 1; - RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix? - RTLIL::Wire *wire = module->wire(wire_name); - if (!wire) - wire = createWireIfNotExists(module, l1); - else if (wire->port_input || wire->port_output) { - RTLIL::Wire *new_wire = module->addWire(NEW_ID); - module->connect(new_wire, wire); - wire = new_wire; - } + RTLIL::Wire *wire = module->addWire(stringf("\\o%0*d", digits, i)); wire->port_output = true; + module->connect(wire, createWireIfNotExists(module, l1)); outputs.push_back(wire); } std::getline(f, line); // Ignore up to start of next line -- cgit v1.2.3 From 0875a078710a2d60ec3c55e9b5a87d97fd643f3b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 17 Dec 2019 15:43:21 -0800 Subject: read_xaiger to cope with optional '\n' after 'c' --- frontends/aiger/aigerparse.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 65a9e30ae..abc2f4144 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -379,8 +379,8 @@ void AigerReader::parse_xaiger(const dict &box_lookup) int c = f.get(); if (c != 'c') log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); - c = f.get(); - log_assert(c == '\n'); + if (f.peek() == '\n') + f.get(); // Parse footer (symbol table, comments, etc.) std::string s; -- cgit v1.2.3 From 5f50e4f1121d139c3c9b842514c86cfc7712b32e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 17 Dec 2019 15:44:35 -0800 Subject: Cleanup xaiger, remove unnecessary complexity with inout --- frontends/aiger/aigerparse.cc | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index abc2f4144..613723966 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -887,16 +887,7 @@ void AigerReader::post_process() // simply connect the latter to the former RTLIL::Wire* existing = module->wire(escaped_s); if (!existing) { - if (escaped_s.ends_with("$inout.out")) { - wire->port_output = false; - RTLIL::Wire *in_wire = module->wire(escaped_s.substr(1, escaped_s.size()-11)); - log_assert(in_wire); - log_assert(in_wire->port_input && !in_wire->port_output); - in_wire->port_output = true; - module->connect(in_wire, wire); - } - else - module->rename(wire, escaped_s); + module->rename(wire, escaped_s); } else { wire->port_output = false; @@ -908,19 +899,9 @@ void AigerReader::post_process() std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); RTLIL::Wire* existing = module->wire(indexed_name); if (!existing) { - if (escaped_s.ends_with("$inout.out")) { - wire->port_output = false; - RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(1, escaped_s.size()-11).c_str(), index)); - log_assert(in_wire); - log_assert(in_wire->port_input && !in_wire->port_output); - in_wire->port_output = true; - module->connect(in_wire, wire); - } - else { - module->rename(wire, indexed_name); - if (wideports) - wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); - } + module->rename(wire, indexed_name); + if (wideports) + wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); } else { module->connect(wire, existing); -- cgit v1.2.3 From a6fdb9f5c1262e57d4aa292778c947773d9fe04d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 17 Dec 2019 15:50:01 -0800 Subject: aiger frontend to user shorter, $-prefixed, names --- frontends/aiger/aigerparse.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 613723966..9cb05dfb3 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -255,7 +255,7 @@ end_of_header: else log_abort(); - RTLIL::Wire* n0 = module->wire("\\__0__"); + RTLIL::Wire* n0 = module->wire("$0"); if (n0) module->connect(n0, State::S0); @@ -316,14 +316,14 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera { const unsigned variable = literal >> 1; const bool invert = literal & 1; - RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); + RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : "")); RTLIL::Wire *wire = module->wire(wire_name); if (wire) return wire; log_debug2("Creating %s\n", wire_name.c_str()); wire = module->addWire(wire_name); wire->port_input = wire->port_output = false; if (!invert) return wire; - RTLIL::IdString wire_inv_name(stringf("\\__%d__", variable)); + RTLIL::IdString wire_inv_name(stringf("$%d", variable)); RTLIL::Wire *wire_inv = module->wire(wire_inv_name); if (wire_inv) { if (module->cell(wire_inv_name)) return wire; @@ -335,7 +335,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera } log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); - module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire); + module->addNotGate(stringf("$%d$not", variable), wire_inv, wire); return wire; } @@ -372,7 +372,7 @@ void AigerReader::parse_xaiger(const dict &box_lookup) else log_abort(); - RTLIL::Wire* n0 = module->wire("\\__0__"); + RTLIL::Wire* n0 = module->wire("$0"); if (n0) module->connect(n0, State::S0); @@ -396,13 +396,13 @@ void AigerReader::parse_xaiger(const dict &box_lookup) uint32_t rootNodeID = parse_xaiger_literal(f); uint32_t cutLeavesM = parse_xaiger_literal(f); log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM); - RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID)); + RTLIL::Wire *output_sig = module->wire(stringf("$%d", rootNodeID)); uint32_t nodeID; RTLIL::SigSpec input_sig; for (unsigned j = 0; j < cutLeavesM; ++j) { nodeID = parse_xaiger_literal(f); log_debug2("\t%u\n", nodeID); - RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID)); + RTLIL::Wire *wire = module->wire(stringf("$%d", nodeID)); log_assert(wire); input_sig.append(wire); } @@ -419,10 +419,10 @@ void AigerReader::parse_xaiger(const dict &box_lookup) log_assert(o.wire == nullptr); lut_mask[gray] = o.data; } - RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID)); + RTLIL::Cell *output_cell = module->cell(stringf("$%d$and", rootNodeID)); log_assert(output_cell); module->remove(output_cell); - module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask)); + module->addLut(stringf("$%d$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask)); } } else if (c == 'r') { @@ -456,7 +456,7 @@ void AigerReader::parse_xaiger(const dict &box_lookup) uint32_t boxUniqueId = parse_xaiger_literal(f); log_assert(boxUniqueId > 0); uint32_t oldBoxNum = parse_xaiger_literal(f); - RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId)); + RTLIL::Cell* cell = module->addCell(stringf("$__box%u", oldBoxNum), box_lookup.at(boxUniqueId)); boxes.emplace_back(cell); } } @@ -544,7 +544,7 @@ void AigerReader::parse_aiger_ascii() log_debug2("%d is an output\n", l1); const unsigned variable = l1 >> 1; const bool invert = l1 & 1; - RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix? + RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix? RTLIL::Wire *wire = module->wire(wire_name); if (!wire) wire = createWireIfNotExists(module, l1); @@ -613,7 +613,7 @@ void AigerReader::parse_aiger_binary() int digits = ceil(log10(I)); for (unsigned i = 1; i <= I; ++i) { log_debug2("%d is an input\n", i); - RTLIL::Wire *wire = module->addWire(stringf("\\i%0*d", digits, i)); + RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i)); wire->port_input = true; module->connect(createWireIfNotExists(module, i << 1), wire); inputs.push_back(wire); @@ -671,7 +671,7 @@ void AigerReader::parse_aiger_binary() log_error("Line %u cannot be interpreted as an output!\n", line_count); log_debug2("%d is an output\n", l1); - RTLIL::Wire *wire = module->addWire(stringf("\\o%0*d", digits, i)); + RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i)); wire->port_output = true; module->connect(wire, createWireIfNotExists(module, l1)); outputs.push_back(wire); @@ -915,7 +915,7 @@ void AigerReader::post_process() wire->attributes["\\init"] = init; } else if (type == "box") { - RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); + RTLIL::Cell* cell = module->cell(stringf("$__box%d", variable)); if (cell) { // ABC could have optimised this box away module->rename(cell, escaped_s); for (const auto &i : cell->connections()) { -- cgit v1.2.3 From e5ed8e8e2172c243bcca651eedd81053a5d7f575 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 16:50:22 -0800 Subject: parse_xaiger to reorder ports too --- frontends/aiger/aigerparse.cc | 67 +++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 41 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 9cb05dfb3..3d00aee10 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -722,6 +722,7 @@ void AigerReader::post_process() { pool seen_boxes; pool flops; + dict> box_ports; unsigned ci_count = 0, co_count = 0, flop_count = 0; for (auto cell : boxes) { RTLIL::Module* box_module = design->module(cell->type); @@ -734,51 +735,35 @@ void AigerReader::post_process() flops.insert(cell->type); is_flop = true; } - auto it = box_module->attributes.find("\\abc9_carry"); - if (it != box_module->attributes.end()) { - RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; - auto carry_in_out = it->second.decode_string(); - auto pos = carry_in_out.find(','); - if (pos == std::string::npos) - log_error("'abc9_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type)); - auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos)); - carry_in = box_module->wire(carry_in_name); - if (!carry_in || !carry_in->port_input) - log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str()); - - auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1)); - carry_out = box_module->wire(carry_out_name); - if (!carry_out || !carry_out->port_output) - log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str()); - - auto &ports = box_module->ports; - for (auto jt = ports.begin(); jt != ports.end(); ) { - RTLIL::Wire* w = box_module->wire(*jt); - log_assert(w); - if (w == carry_in || w == carry_out) { - jt = ports.erase(jt); - continue; - } - if (w->port_id > carry_in->port_id) - --w->port_id; - if (w->port_id > carry_out->port_id) - --w->port_id; - log_assert(w->port_input || w->port_output); - log_assert(ports[w->port_id-1] == w->name); - ++jt; - } - ports.push_back(carry_in->name); - carry_in->port_id = ports.size(); - ports.push_back(carry_out->name); - carry_out->port_id = ports.size(); - } } else is_flop = flops.count(cell->type); - // NB: Assume box_module->ports are sorted alphabetically - // (as RTLIL::Module::fixup_ports() would do) - for (auto port_name : box_module->ports) { + auto r = box_ports.insert(cell->type); + if (r.second) { + // Make carry in the last PI, and carry out the last PO + // since ABC requires it this way + IdString carry_in, carry_out; + for (const auto &port_name : box_module->ports) { + auto w = box_module->wire(port_name); + log_assert(w); + if (w->get_bool_attribute("\\abc9_carry")) { + if (w->port_input) + carry_in = port_name; + if (w->port_output) + carry_out = port_name; + } + else + r.first->second.push_back(port_name); + } + if (carry_in != IdString()) { + log_assert(carry_out != IdString()); + r.first->second.push_back(carry_in); + r.first->second.push_back(carry_out); + } + } + + for (auto port_name : box_ports.at(cell->type)) { RTLIL::Wire* port = box_module->wire(port_name); log_assert(port); RTLIL::SigSpec rhs; -- cgit v1.2.3 From 96db05aaefd970c819ba1f75b7246c5958527b8b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 17:06:03 -0800 Subject: parse_xaiger to not take box_lookup --- frontends/aiger/aigerparse.cc | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) (limited to 'frontends/aiger/aigerparse.cc') diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 3d00aee10..f030933ec 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -340,7 +340,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera return wire; } -void AigerReader::parse_xaiger(const dict &box_lookup) +void AigerReader::parse_xaiger() { std::string header; f >> header; @@ -382,6 +382,21 @@ void AigerReader::parse_xaiger(const dict &box_lookup) if (f.peek() == '\n') f.get(); + dict box_lookup; + for (auto m : design->modules()) { + auto it = m->attributes.find(ID(abc9_box_id)); + if (it == m->attributes.end()) + continue; + if (m->name.begins_with("$paramod")) + continue; + auto id = it->second.as_int(); + auto r = box_lookup.insert(std::make_pair(id, m->name)); + if (!r.second) + log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n", + log_id(m), id, log_id(r.first->second)); + log_assert(r.second); + } + // Parse footer (symbol table, comments, etc.) std::string s; for (int c = f.get(); c != EOF; c = f.get()) { @@ -456,7 +471,7 @@ void AigerReader::parse_xaiger(const dict &box_lookup) uint32_t boxUniqueId = parse_xaiger_literal(f); log_assert(boxUniqueId > 0); uint32_t oldBoxNum = parse_xaiger_literal(f); - RTLIL::Cell* cell = module->addCell(stringf("$__box%u", oldBoxNum), box_lookup.at(boxUniqueId)); + RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), box_lookup.at(boxUniqueId)); boxes.emplace_back(cell); } } @@ -720,25 +735,12 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { - pool seen_boxes; - pool flops; dict> box_ports; unsigned ci_count = 0, co_count = 0, flop_count = 0; for (auto cell : boxes) { RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); - bool is_flop = false; - if (seen_boxes.insert(cell->type).second) { - if (box_module->attributes.count("\\abc9_flop")) { - log_assert(flop_count < flopNum); - flops.insert(cell->type); - is_flop = true; - } - } - else - is_flop = flops.count(cell->type); - auto r = box_ports.insert(cell->type); if (r.second) { // Make carry in the last PI, and carry out the last PO @@ -788,7 +790,7 @@ void AigerReader::post_process() cell->setPort(port_name, rhs); } - if (is_flop) { + if (box_module->attributes.count("\\abc9_flop")) { log_assert(co_count < outputs.size()); Wire *wire = outputs[co_count++]; log_assert(wire); @@ -900,7 +902,7 @@ void AigerReader::post_process() wire->attributes["\\init"] = init; } else if (type == "box") { - RTLIL::Cell* cell = module->cell(stringf("$__box%d", variable)); + RTLIL::Cell* cell = module->cell(stringf("$box%d", variable)); if (cell) { // ABC could have optimised this box away module->rename(cell, escaped_s); for (const auto &i : cell->connections()) { -- cgit v1.2.3