From 161565be104fd0c7b7c4224bd23e9502625e041a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 31 Mar 2013 11:19:11 +0200
Subject: Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)

---
 frontends/ast/genrtlil.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'frontends/ast/genrtlil.cc')

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 47ca37bd0..2f5370fe8 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -310,6 +310,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 		case AST_COND:
 		case AST_ALWAYS:
+		case AST_INITIAL:
 			for (auto child : ast->children)
 				if (child->type == AST_BLOCK)
 					collect_lvalues(reg, child, type_eq, type_le, false);
@@ -1013,7 +1014,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
 		break;
 
 	// use ProcessGenerator for always blocks
-	case AST_ALWAYS: {
+	case AST_ALWAYS:
+	case AST_INITIAL: {
 			AstNode *always = this->clone();
 			ProcessGenerator generator(always);
 			delete always;
-- 
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