From 999eec561752706a8ccb085a692684c745415985 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Tue, 22 Dec 2020 17:38:51 -0700 Subject: genrtlil: fix mux2rtlil generated wire signedness --- frontends/ast/genrtlil.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/ast') diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 500ccf8c0..b8bfdf65e 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -141,6 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); + wire->is_signed = that->is_signed; for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) -- cgit v1.2.3