From 96f64f4788ca64adde55421a6abadefd182d9a1a Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 3 May 2022 13:22:18 +0200 Subject: verific: Fix conditions of SVAs with explicit clocks within procedures For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case. --- frontends/verific/verific.h | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verific/verific.h') diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 416b26396..695c04f3b 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -44,6 +44,7 @@ struct VerificClocking { SigBit disable_sig = State::S0; bool posedge = true; bool gclk = false; + bool cond_pol = true; VerificClocking() { } VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false); -- cgit v1.2.3