From 91dd87e60b120119ee34a9961a7b5f33f340282e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 5 Aug 2014 12:15:53 +0200 Subject: Improved scope resolution of local regs in Verilog+AST frontend --- frontends/verilog/parser.y | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'frontends/verilog/parser.y') diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 1e0168a5f..26e2ddc34 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -599,12 +599,11 @@ wire_name: if (node->is_input || node->is_output) frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str()); } - ast_stack.back()->children.push_back(node); } else { if (node->is_input || node->is_output) node->port_id = current_function_or_task_port_id++; - current_function_or_task->children.push_back(node); } + ast_stack.back()->children.push_back(node); delete $1; }; -- cgit v1.2.3