From 0bc95f1e049afc35bb5ea30663b0a5725dfbf584 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Apr 2016 23:28:37 +0200 Subject: Added "yosys -D" feature --- frontends/verilog/verilog_frontend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verilog/verilog_frontend.cc') diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 11c2824c3..f8ccda181 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -186,7 +186,7 @@ struct VerilogFrontend : public Frontend { formal_mode = false; default_nettype_wire = true; - log_header("Executing Verilog-2005 frontend.\n"); + log_header(design, "Executing Verilog-2005 frontend.\n"); args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); -- cgit v1.2.3