From 416a66aee822c999a28f580cbcdb24cdf4e73a13 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Wed, 3 Jun 2020 13:51:57 +0200 Subject: Add or-assignment operator Signed-off-by: Kamil Rakoczy --- frontends/verilog/verilog_lexer.l | 2 ++ 1 file changed, 2 insertions(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index e6fa6361e..ea85bf52e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -526,6 +526,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { ".*" { return TOK_WILDCARD_CONNECT; } +"|=" { SV_KEYWORD(TOK_OR_ASSIGN); } + [-+]?[=*]> { if (!specify_mode) REJECT; yylval->string = new std::string(yytext); -- cgit v1.2.3 From 22408f24c7d9c8a648e854fad01aff37a0f9fbd9 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Wed, 3 Jun 2020 16:44:02 +0200 Subject: Add plus-assignment operator Signed-off-by: Kamil Rakoczy --- frontends/verilog/verilog_lexer.l | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index ea85bf52e..c77da4274 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -527,6 +527,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { ".*" { return TOK_WILDCARD_CONNECT; } "|=" { SV_KEYWORD(TOK_OR_ASSIGN); } +"+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); } [-+]?[=*]> { if (!specify_mode) REJECT; -- cgit v1.2.3 From a4b4c22c962e2971a093da9cf2364ec19050dd32 Mon Sep 17 00:00:00 2001 From: Lukasz Dalek Date: Tue, 23 Jun 2020 18:50:50 +0200 Subject: Support missing xor-assign operator Signed-off-by: Lukasz Dalek --- frontends/verilog/verilog_lexer.l | 1 + 1 file changed, 1 insertion(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index c77da4274..8c9f403a3 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -528,6 +528,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { "|=" { SV_KEYWORD(TOK_OR_ASSIGN); } "+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); } +"^=" { SV_KEYWORD(TOK_XOR_ASSIGN); } [-+]?[=*]> { if (!specify_mode) REJECT; -- cgit v1.2.3 From 539087f417e08c56e47b8289ec65d418f7d14792 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Thu, 25 Jun 2020 13:29:06 +0200 Subject: Support missing sub-assign and and-assign operators Signed-off-by: Kamil Rakoczy --- frontends/verilog/verilog_lexer.l | 2 ++ 1 file changed, 2 insertions(+) (limited to 'frontends/verilog/verilog_lexer.l') diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8c9f403a3..028106381 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -527,7 +527,9 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { ".*" { return TOK_WILDCARD_CONNECT; } "|=" { SV_KEYWORD(TOK_OR_ASSIGN); } +"&=" { SV_KEYWORD(TOK_AND_ASSIGN); } "+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); } +"-=" { SV_KEYWORD(TOK_SUB_ASSIGN); } "^=" { SV_KEYWORD(TOK_XOR_ASSIGN); } [-+]?[=*]> { -- cgit v1.2.3