From 34d4e72132863279187950de259fb112ca749787 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 23 Feb 2017 11:21:33 +0100 Subject: Added SystemVerilog support for ++ and -- --- frontends/verilog/verilog_parser.y | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 1879ff441..7c2880e4e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -117,6 +117,7 @@ static void free_attr(std::map *al) %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME %token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER +%token TOK_INCREMENT TOK_DECREMENT %type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int %type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list @@ -1067,6 +1068,14 @@ simple_behavioral_stmt: AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4); ast_stack.back()->children.push_back(node); } | + lvalue TOK_INCREMENT { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true))); + ast_stack.back()->children.push_back(node); + } | + lvalue TOK_DECREMENT { + AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true))); + ast_stack.back()->children.push_back(node); + } | lvalue OP_LE delay expr { AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4); ast_stack.back()->children.push_back(node); -- cgit v1.2.3 From 00dba4c197b7e3b6c1d1f7b90ae7b1e6172b1e5f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 23 Feb 2017 16:33:19 +0100 Subject: Add support for SystemVerilog unique, unique0, and priority case --- frontends/verilog/verilog_parser.y | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 7c2880e4e..9b2498694 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -117,13 +117,13 @@ static void free_attr(std::map *al) %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME %token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER -%token TOK_INCREMENT TOK_DECREMENT +%token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY %type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int %type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type opt_label tok_prim_wrapper hierarchical_id -%type opt_signed -%type attr +%type opt_signed unique_case_attr +%type attr case_attr // operator precedence from low to high %left OP_LOR @@ -1167,7 +1167,7 @@ behavioral_stmt: ast_stack.pop_back(); ast_stack.pop_back(); } | - attr case_type '(' expr ')' { + case_attr case_type '(' expr ')' { AstNode *node = new AstNode(AST_CASE, $4); ast_stack.back()->children.push_back(node); ast_stack.push_back(node); @@ -1177,6 +1177,23 @@ behavioral_stmt: ast_stack.pop_back(); }; +unique_case_attr: + /* empty */ { + $$ = false; + } | + TOK_PRIORITY case_attr { + $$ = $2; + } | + TOK_UNIQUE case_attr { + $$ = true; + }; + +case_attr: + attr unique_case_attr { + if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false); + $$ = $1; + }; + case_type: TOK_CASE { case_type_stack.push_back(0); -- cgit v1.2.3