From 1096b969efb24dc28b501585f23ceb242d781745 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 21 Jan 2021 08:30:55 -0700 Subject: Allow combination of rand and const modifiers --- frontends/verilog/verilog_parser.y | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 2886db0e5..8bd58d24c 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -651,8 +651,16 @@ wire_type_signedness: %empty; wire_type_const_rand: - TOK_CONST { current_wire_const = true; } | - TOK_RAND { current_wire_rand = true; } | + TOK_RAND TOK_CONST { + current_wire_rand = true; + current_wire_const = true; + } | + TOK_CONST { + current_wire_const = true; + } | + TOK_RAND { + current_wire_rand = true; + } | %empty; opt_wire_type_token: -- cgit v1.2.3