From 28cfc75a902574c3ad96876d2f5e01af6c583bac Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Wed, 15 Aug 2018 19:56:30 +0300 Subject: A few minor enhancements to specify block parsing. Just remember specify blocks are parsed but ignored. --- frontends/verilog/verilog_parser.y | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 78cac5543..61da12b76 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -688,8 +688,8 @@ path_declaration : ; simple_path_declaration : - parallel_path_description '=' path_delay_value ';' - // | full_path_description '=' path_delay_value ';' + parallel_path_description '=' path_delay_value ';' | + full_path_description '=' path_delay_value ';' ; path_delay_value : @@ -723,6 +723,17 @@ list_of_path_delay_expressions : parallel_path_description : '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; +full_path_description : + '(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ; + +list_of_path_inputs : + specify_input_terminal_descriptor | + list_of_path_inputs ',' specify_input_terminal_descriptor ; + +list_of_path_outputs : + specify_output_terminal_descriptor | + list_of_path_outputs ',' specify_output_terminal_descriptor ; + opt_polarity_operator : '+' | '-' -- cgit v1.2.3 From 95241c8f4d32c5bd644bef71509965a82582264c Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Mon, 20 Aug 2018 00:08:08 +0300 Subject: Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value. --- frontends/verilog/verilog_parser.y | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 61da12b76..58a6824d1 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -654,7 +654,7 @@ specify_item: // | pulsestyle_declaration // | showcancelled_declaration | path_declaration - // | system_timing_declaration + | system_timing_declaration ; specparam_declaration: @@ -693,8 +693,8 @@ simple_path_declaration : ; path_delay_value : - //list_of_path_delay_expressions - '(' list_of_path_delay_expressions ')' + list_of_path_delay_expressions | + %prec '(' list_of_path_delay_expressions ')' ; list_of_path_delay_expressions : @@ -724,12 +724,17 @@ parallel_path_description : '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; full_path_description : - '(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ; + '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ; +// This was broken into 2 rules to solve shift/reduce conflicts list_of_path_inputs : - specify_input_terminal_descriptor | - list_of_path_inputs ',' specify_input_terminal_descriptor ; - + specify_input_terminal_descriptor opt_polarity_operator | + specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ; + +more_path_inputs : + ',' specify_input_terminal_descriptor | + more_path_inputs ',' specify_input_terminal_descriptor ; + list_of_path_outputs : specify_output_terminal_descriptor | list_of_path_outputs ',' specify_output_terminal_descriptor ; @@ -747,11 +752,18 @@ specify_input_terminal_descriptor : specify_output_terminal_descriptor : TOK_ID ; -/* system_timing_declaration : - ; -*/ + TOK_ID '(' system_timing_args ')' ';' ; + +system_timing_arg : + TOK_POSEDGE TOK_ID | + TOK_NEGEDGE TOK_ID | + expr ; +system_timing_args : + system_timing_arg | + system_timing_args ',' system_timing_arg ; + /* t_path_delay_expression : path_delay_expression; -- cgit v1.2.3 From fbfc677df3e54798faba3ab2f27c270759b96507 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Mon, 20 Aug 2018 17:27:45 +0300 Subject: Fixed all known specify/endspecify issues, without breaking 'make test'. Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses --- frontends/verilog/verilog_parser.y | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 58a6824d1..2389d7d31 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -682,22 +682,23 @@ showcancelled_declaration : */ path_declaration : - simple_path_declaration + simple_path_declaration ';' // | edge_sensitive_path_declaration // | state_dependent_path_declaration ; simple_path_declaration : - parallel_path_description '=' path_delay_value ';' | - full_path_description '=' path_delay_value ';' + parallel_path_description '=' path_delay_value | + full_path_description '=' path_delay_value ; path_delay_value : - list_of_path_delay_expressions | - %prec '(' list_of_path_delay_expressions ')' + '(' path_delay_expression list_of_path_delay_extra_expressions ')' + | path_delay_expression + | path_delay_expression list_of_path_delay_extra_expressions ; -list_of_path_delay_expressions : +list_of_path_delay_extra_expressions : /* t_path_delay_expression | trise_path_delay_expression ',' tfall_path_delay_expression @@ -709,12 +710,11 @@ list_of_path_delay_expressions : t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ',' tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression */ - path_delay_expression - | path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + ',' path_delay_expression + | ',' path_delay_expression ',' path_delay_expression + | ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + | ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression @@ -815,7 +815,7 @@ tzx_path_delay_expression : */ path_delay_expression : - constant_mintypmax_expression; + constant_expression; constant_mintypmax_expression : constant_expression -- cgit v1.2.3 From eb452ffb2861ceac572a4bef6dddb8db3b79deb7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 23 Sep 2018 10:32:54 +0200 Subject: Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_parser.y | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 2389d7d31..63cf646e9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -881,9 +881,15 @@ param_decl_list: single_param_decl: TOK_ID '=' expr { - if (astbuf1 == nullptr) - frontend_verilog_yyerror("syntax error"); - AstNode *node = astbuf1->clone(); + AstNode *node; + if (astbuf1 == nullptr) { + if (!sv_mode) + frontend_verilog_yyerror("syntax error"); + node = new AstNode(AST_PARAMETER); + node->children.push_back(AstNode::mkconst_int(0, true)); + } else { + node = astbuf1->clone(); + } node->str = *$1; delete node->children[0]; node->children[0] = $3; -- cgit v1.2.3 From 8fde05dfa58d87ff2e71495c77f698af19a0d80b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 24 Sep 2018 20:51:16 +0200 Subject: Add "read_verilog -noassert -noassume -assert-assumes" Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_parser.y | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 63cf646e9..16cac1460 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -58,7 +58,8 @@ namespace VERILOG_FRONTEND { bool do_not_require_port_stubs; bool default_nettype_wire; bool sv_mode, formal_mode, lib_mode; - bool norestrict_mode, assume_asserts_mode; + bool noassert_mode, noassume_mode, norestrict_mode; + bool assume_asserts_mode, assert_assumes_mode; bool current_wire_rand, current_wire_const; std::istream *lexin; } @@ -1281,16 +1282,28 @@ opt_stmt_label: assert: opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5)); + if (noassert_mode) + delete $5; + else + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5)); } | opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5)); + if (noassume_mode) + delete $5; + else + ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5)); } | opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6)); + if (noassert_mode) + delete $6; + else + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6)); } | opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6)); + if (noassume_mode) + delete $6; + else + ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6)); } | opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5)); -- cgit v1.2.3