From 5df591c02309c086229029808c21ab8721278888 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 22 Nov 2019 09:04:54 +0000 Subject: hierarchy: Resolve SV wildcard port connections Signed-off-by: David Shah --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'frontends/verilog/verilog_parser.y') diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index cb413e13a..5ec8e66a6 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1582,7 +1582,7 @@ cell_port: free_attr($1); } | attr TOK_AUTOCONNECT_ALL { - astbuf2->attributes[ID(autoconnect)] = AstNode::mkconst_int(1, false); + astbuf2->attributes[ID(implicit_port_conns)] = AstNode::mkconst_int(1, false); }; always_comb_or_latch: -- cgit v1.2.3