From 9c120b89ace6c111aa4677616947d18d980b9c1a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 9 Jul 2020 18:13:04 +0000
Subject: Revert PRs #2203 and #2244.
This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15.
This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405.
This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3.
This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68.
This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
---
frontends/verilog/verilog_parser.y | 29 ++++++++++-------------------
1 file changed, 10 insertions(+), 19 deletions(-)
(limited to 'frontends/verilog/verilog_parser.y')
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index dfdb11cf0..0fdf2b516 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -747,7 +747,7 @@ module_body:
module_body_stmt:
task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
enum_decl | struct_decl |
- always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
+ always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
checker_decl:
TOK_CHECKER TOK_ID ';' {
@@ -1331,45 +1331,36 @@ ignspec_id:
param_signed:
TOK_SIGNED {
astbuf1->is_signed = true;
- } | TOK_UNSIGNED {
- astbuf1->is_signed = false;
} | /* empty */;
param_integer:
TOK_INTEGER {
+ if (astbuf1->children.size() != 1)
+ frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
astbuf1->children.push_back(new AstNode(AST_RANGE));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
astbuf1->is_signed = true;
- }
+ } | /* empty */;
param_real:
TOK_REAL {
+ if (astbuf1->children.size() != 1)
+ frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
astbuf1->children.push_back(new AstNode(AST_REALVALUE));
- }
-
-param_logic:
- TOK_LOGIC {
- // SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned
- astbuf1->is_signed = false;
- astbuf1->is_logic = true;
- }
+ } | /* empty */;
param_range:
range {
if ($1 != NULL) {
+ if (astbuf1->children.size() != 1)
+ frontend_verilog_yyerror("integer/real parameters should not have a range.");
astbuf1->children.push_back($1);
}
};
-param_integer_type: param_integer param_signed
-param_range_type: type_vec param_signed param_range
-param_implicit_type: param_signed param_range
-
-param_integer_vector_type: param_logic param_signed param_range
-
param_type:
- param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type |
+ param_signed param_integer param_real param_range |
hierarchical_type_id {
astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
--
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