From a862642fac5d5b7700b2e13829a411f2755273a0 Mon Sep 17 00:00:00 2001
From: Dag Lem <dag@nimrod.no>
Date: Sun, 13 Nov 2022 07:41:25 +0100
Subject: Correct interpretation of SystemVerilog C-style array dimensions
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IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].
---
frontends/verilog/verilog_parser.y | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
(limited to 'frontends/verilog/verilog_parser.y')
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index c533b0c40..70ee47561 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -229,9 +229,9 @@ static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
static void rewriteRange(AstNode *rangeNode)
{
if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
- // SV array size [n], rewrite as [n-1:0]
- rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
- rangeNode->children.push_back(AstNode::mkconst_int(0, false));
+ // SV array size [n], rewrite as [0:n-1]
+ rangeNode->children.push_back(new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)));
+ rangeNode->children[0] = AstNode::mkconst_int(0, false);
}
}
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